Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems 2014
DOI: 10.1145/2609248.2609256
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A framework for dynamic parallelization of FPGA-accelerated applications

Abstract: High-level synthesis and compiler studies have introduced many compile-time techniques for parallelizing applications. However, one fundamental limitation of compile-time optimization is the requirement for pessimistic dependence assumptions that can significantly restrict parallelism. To avoid this limitation, many compilers require a restrictive coding style that is not practical for many designers. We present a more transparent approach that aggressively parallelizes applications by dynamically analyzing ac… Show more

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