The Quartus University Interface Program: enabling advanced FPGA research

Malhotra, Shivani; Borer, Terry; Singh, Deshanand P.; Brown, Stephen D.

doi:10.1109/fpt.2004.1393272

Cited by 15 publications

(8 citation statements)

References 16 publications

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“…where academic tools can be tested [6]. Because SIS lacks HDL elaboration, a parser has been created to implement a VQM netlist in SIS internal representation.…”

Section: Resultsmentioning

confidence: 99%

Beyond the arithmetic constraint

Frederick

Somani

2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

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Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose processors and ASICs alike. One way architects have bridged the performance gap between FPGAs and ASICs is through the inclusion of specialized components such as multipliers, RAM modules, and microcontrollers. Another dedicated structure that has become standard in reconfigurable fabrics is the arithmetic carry chain. Currently, it is only used to map arithmetic operations as identified by HDL macros. For non-arithmetic operations, it is an idle but potentially powerful resource.This work presents ChainMap, a polynomial-time delayoptimal technology mapping algorithm for the creation of generic logic chains in LUT-based FPGAs. ChainMap requires no HDL macros be preserved through the design flow. It creates logic chains, both arithmetic and non-arithmetic, in an arbitrary Boolean network whenever depth increasing nodes are encountered. Use of the chain is not reserved for arithmetic, but rather any set of gates exhibiting similar characteristics. By using the carry chain as a generic, near zero-delay adjacent cell interconnection structure an average optimal speedup of 1.4x is revealed, and an average relaxed speedup of 1.25x can be realized simultaneously with a 0.95x LUT utilization decrease.

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“…where academic tools can be tested [6]. Because SIS lacks HDL elaboration, a parser has been created to implement a VQM netlist in SIS internal representation.…”

Section: Resultsmentioning

confidence: 99%

Beyond the arithmetic constraint

Frederick

Somani

2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

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“…Considering that the Modelsim software can merely achieve functional simulation of the circuit design and the simulated results can not truly reflect the circuit hardware, it is necessary to conduct timing simulation using Quartus II in order to make the design closer to the real circuits [9].…”

Section: Timing Simulation Using Quartus IImentioning

confidence: 99%

IIR Digital Filter Design Based on DSP and SOPC

Zhang

Pan

Ding

2010

2010 International Symposium on Intelligence Information Processing and Trusted Computing

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A design of IIR digital filter based on DSP and SOPC technology was respectively conducted in this paper. Then design principles and implementation schemes were put forward, and the schematics of the hardware circuits as well as the software flow chart were given in detail. The experimental results indicate that the SOPC design has the advantages of flexible controls, continuous output phase, high precision, high reliability, and that it has better application value compared with the method by using the DSP chip under the integrated development environment CCS (code composer studio).

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“…This paper reviews recent advances in FPGA reverse engineering, particularly those using Xilinx FPGA products that occupy a dominant portion in FPGA markets, and also discusses their performance and limitations through hands-on experiments. In addition, this paper also reviews several supplementary tools that can support the reverse engineering [13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Recent Advances in FPGA Reverse Engineering

Lee

et al. 2018

Electronics

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In this paper, we review recent advances in reverse engineering with an emphasis on FPGA devices and experimentally verified advantages and limitations of reverse engineering tools. The paper first introduces essential components for programming Xilinx FPGAs (Xilinx, San Jose, CA, USA), such as Xilinx Design Language (XDL), XDL Report (XDLRC), and bitstream. Then, reverse engineering tools (Debit, BIL, and Bit2ncd), which extract the bitstream from the external memory to the FPGA and utilize it to recover the netlist, are reviewed, and their limitations are discussed. This paper also covers supplementary tools (Rapidsmith) that can adjust the FPGA design flow to support reverse engineering. Finally, reverse engineering projects for non-Xilinx products, such as Lattice FPGAs (Icestorm) and Altera FPGAs (QUIP), are introduced to compare the reverse engineering capabilities by various commercial FPGA products.

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The Quartus University Interface Program: enabling advanced FPGA research

Cited by 15 publications

References 16 publications

Beyond the arithmetic constraint

Beyond the arithmetic constraint

IIR Digital Filter Design Based on DSP and SOPC

Recent Advances in FPGA Reverse Engineering

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