The Priority Division Arbiter for low WCET and high Resource Utilization in Multi-core Architectures

Abstract

Shared memory arbiters play a major role in determining the Worst Case Execution Time (Wcet) of applications executing on multi-core architectures. Apart from the produced Wcet, shared memory utilization is another important parameter which characterizes the suitability of an arbiter for a particular system. This paper compares the traditional arbiters, the Static priority (aka fixed priority), the Time Division Multiple Access (Tdma) and the Round robin against the Priority division arbiter on the above mentioned merits. The paper extends the Priority division arbiter by providing a new configuration, called h1, which is highly attractive for mixed critical systems with a single Hard Real-Time (Hrt) application. The paper derives formulas to calculate the worst case latency and the worst case memory utilization. The analysis proves that the Priority division arbiter outperforms the Tdma arbiter in memory utilization and the Round robin arbiter in the produced Wcet. Moreover, the Priority division arbiter, under the h1 mode, outperforms the Static priority arbiter in terms of the produced Wcet of the single Hrt application. The supporting evidences are achieved by conducting experiments on a quad-core NIOS architecture built on Altera Fpga. The test applications are chosen from the Mälardalen Wcet benchmark suit.

Measurement based WCET Analysis for Multi-core Architectures

“…Additionally, the synthetic code to create the interference is trivial, change in architecture is not at all required and hybrid Wcet analysis technique for single core architectures can be used for multi-cores without any modification. However, as shown in our previous work [26], this technique neither guarantees the worst case interference nor the worst case execution time except under the Priority Division [22] arbiter.…”

“…Test applications are chosen from the Mälardalen Wcet benchmark suit [10]. We typically chose the multi-path applications from the suit since the single path applications are already tested in our another work [22]. For testing purpose, we used the optimized version (Sec.…”

A Performance Conserving Approach for Reducing Memory Power Consumption in Multi-Core Systems

“…Shah et al discuss the use of timing analysis to limit the interference between applications in shared resources. 3,4 Bank partitioning 5,6 maps memory accesses from di®erent cores to different banks, which isolates the memory access streams from di®erent cores and effectively eliminates the interference. In bank partitioning, one core can only access its speci¯c banks and the number of banks that each core owns is equal.…”