2014 IEEE International Parallel &Amp; Distributed Processing Symposium Workshops 2014
DOI: 10.1109/ipdpsw.2014.162
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The Power-Performance Tradeoffs of the Intel Xeon Phi on HPC Applications

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Cited by 25 publications
(21 citation statements)
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“…The work distribution at 240 threads is too fine-grain to hide the runtime overheads of these implementations, while the lightweight runtime of SWITCHES achieves the highest performance at 240 threads. Oversubscribing the Xeon Phi to 300 and 360 threads results in degraded performance as it can cause higher resource contention and pipeline latencies [33].…”
Section: Data-parallel Applicationmentioning
confidence: 99%
“…The work distribution at 240 threads is too fine-grain to hide the runtime overheads of these implementations, while the lightweight runtime of SWITCHES achieves the highest performance at 240 threads. Oversubscribing the Xeon Phi to 300 and 360 threads results in degraded performance as it can cause higher resource contention and pipeline latencies [33].…”
Section: Data-parallel Applicationmentioning
confidence: 99%
“…These benchmarks, which use algorithms in various domains to stress different processor components, have been used in several studies of accelerators. For example, [9] compares the many-core Intel R Xeon Phi TM to the Intel R Sandy Bridge Xeon E5-2620 multi-core processor and the manycore NVIDIA Tesla c2050 GPU (which employs the Fermi architecture). The SHOC benchmarks are used to compare the Phi TM with the Tesla in terms of power consumption and execution time, while the Rodinia benchmarks are used to compare the Phi TM to the Sandy Bridge in terms of execution time.…”
Section: Related Workmentioning
confidence: 99%
“…An initial validation of the model is performed using either single-or multi-node computing platforms running the CoMD proxy application for molecular dynamics simulations [17,7]. Other related work on modeling and performance profiling of the Xeon Phi has been conducted in [18] and [16]. However, those research efforts do not combine the accelerator execution modes with the host operation, as proposed here for heterogeneous architectures with accelerators used to offload computations from the host CPU.…”
Section: Related Workmentioning
confidence: 99%