Modeling performance and energy for applications offloaded to Intel Xeon Phi

Abstract

Accelerators are adopted to increase performance, reduce time-to-solution, and minimize energy-to-solution. However, employing them efficiently, given system and application characteristics, is often a daunting task. A goal of this work is to propose a general model that predicts performance and power requirements for an application, computational portions of which are offloaded to an accelerator. Intel Xeon Phi is the only accelerator type investigated here, and only in offload execution mode. This mode is also employed by other accelerator types, such as GPU; thus the proposed model is applicable directly. The predictive capabilities of the model are demonstrated by determining the best hardware-software configuration instances with respect to the minimum energy consumption for the CoMD proxy application executed on single or multiple nodes. For the CoMD problem sizes investigated here, the best modeled configuration was relatively close to the best measured configuration with relative error under 5% of the energy consumed for most configurations. Initial model validation also confirmed the model accuracy for a variety of model parameters, such as host computation time and power consumption on the host and accelerator. The model also provides estimates of the total data movement and computational throughput as well as of some key metrics, such as FLOPs- * Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from Permissions@acm.org. Co-HPC2015, November 15-20, 2015, Austin, TX, USA c 2015 ACM. ISBN 978-1-4503-3992-6/15/11$15.00 DOI: http://dx.

Applying EMD/HHT analysis to power traces of applications executed on systems with Intel Xeon Phi

“…Phase refers to a computation or data movement type operation, such as RAM to cache data transfers or communication on the node or over the network; the phases often overlap to optimize performance. Such a division was considered by Lawson et al (2015) in order to model each phase differently, which has proven to be difficult in general for correlating phases with power readings. The implementation of the EMD/HHT method used here is based on the original one from Huang et al (1998) and Wu and Huang (2009), as adapted by Ezer and Corlett (2012) and Ezer et al (2013), and the code for EMD/HHT analysis is available in the study by Ezer (2015) in MATLAB.…”

“…For KNC-native, the flag is required. The CPU-KNC offload usage mode was developed by the authors, see the previous work for details on the offload usage mode (Lawson et al, 2014, 2015).…”

The Power-optimised Software Envelope

“…Early versions of RAPL were model based, but more recent processors incorporate dedicated power sensors. AMD included equivalent functionality starting with their Bulldozer CPU [1], while similar schemes exist for GPU [8] and Xeon Phi [28] platforms.…”