The Potential Energy Efficiency of Vector Acceleration

Lemuet,; Sampson,; François,; Jouppi,

doi:10.1109/sc.2006.62

Cited by 15 publications

(13 citation statements)

References 15 publications

(14 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since vector processors are by default energy-e cient (Lemuet et al 2006), we added support for vector instructions. We did not consider adding multiple lanes due to the following reasons: (1) we wanted to do minimal changes to the existing scalar processor in order to keep the area/power envelope and reuse the existing processor resources in the most e cient way; (2) adding one additional lane increases area of scalar baseline by 44%; adding four lanes will more than double the area of the processor and it is not acceptable in highly constrained low-end devices.…”

Section: Related Workmentioning

confidence: 99%

An Integrated Vector-Scalar Design on an In-Order ARM Core

Stanić

Palomar

Hayes

et al. 2017

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

In the low-end mobile processor market, power, energy and area budgets are signi cantly lower than in the server/desktop/laptop/high-end mobile markets. It has been shown that vector processors are a highly energy-e cient way to increase performance; however adding support for them incurs area and power overheads that would not be acceptable for low-end mobile processors. In this work, we propose an integrated vector-scalar design for the ARM architecture that mostly reuses scalar hardware to support the execution of vector instructions. The key element of the design is our proposed block-based model of execution that groups vector computational instructions together to execute them in a coordinated manner. We implemented a classic vector unit and compare its results against our integrated design. Our integrated design improves the performance (more than 6x) and energy consumption (up to 5x) of a scalar in-order core with negligible area overhead (only 4.7% when using a vector register with 32 elements). In contrast, the area overhead of the classic vector unit can be signi cant (around 44%) if a dedicated vector oating-point unit is incorporated. Our block-based vector execution outperforms the classic vector unit for all kernels with oating-point data and also consumes less energy. We also complement the integrated design with three energy-performance e cient techniques that further reduce power and increase performance. The rst proposal covers the design and implementation of chaining logic that is optimized to work with the cache hierarchy through vector memory instructions, the second proposal reduces number of reads/writes from/to the vector register le while the third idea optimizes complex memory access patterns with the memory shape instruction and uni ed indexed vector load. The research leading to these results has received funding from the RoMoL ERC Advanced Grant GA no 321253 and is supported in part by the European Union (FEDER funds) under contract TIN2015-65316-P. This research has been also supported the Agency for Management of University and Research Grants (AGAUR -FI-DGR 2014). O. Palomar is funded by a Royal Society Newton International Fellowship. Current author's a liations: M. Stanic, ASML; O. Palomar, University of Manchester; T. Hayes, ARM. A. Cristal is also a liated with CSIC-IIIA and UPC. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro t or commercial advantage and that copies bear this notice and the full citation on the rst page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior speci c permission and/or a fee. Request permissions from permissions@acm.org. INTRODUCTIONIn the last 15 years, power dissipation and energy consumption have become crucial design concerns for almost all...

show abstract

Section: Related Workmentioning

confidence: 99%

An Integrated Vector-Scalar Design on an In-Order ARM Core

Stanić

Palomar

Hayes

et al. 2017

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

show abstract

“…The vector architectures are compared with conventional superscalar and VLIW architectures for multimedia benchmarks in [74]. Energy-efficiency potentials of vector accelerators for high performance computing systems are discussed in [86]. The efficiency of an architecture depends on the organization of the SIMD units and how they are employed with regard to instruction pipeline and memory hierarchy.…”

Section: Simd Alus and Vector Processorsmentioning

confidence: 99%

Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics

Pedram

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

View full text Add to dashboard Cite

“…Energyefficiency potentials of vector accelerators for high performance computing systems are discussed in [28]. Three main limitations of conventional 1D vector architectures are known to be complexity of the central register file, implementation difficulties of precise exception handling, and expensive onchip memory [20].…”

Section: B Related Workmentioning

confidence: 99%

On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators

Pedram

Gerstlauer

Geijn

2012

2012 IEEE 24th International Symposium on Computer Architecture and High Performance Computing

View full text Add to dashboard Cite

Abstract-Reducing power consumption and increasing efficiency is a key concern for many applications. How to design highly efficient computing elements while maintaining enough flexibility within a domain of applications is a fundamental question. In this paper, we present how broadcast buses can eliminate the use of power hungry multi-ported register files in the context of data-parallel hardware accelerators for linear algebra operations. We demonstrate an algorithm/architecture co-design for the mapping of different collective communication operations, which are crucial for achieving performance and efficiency in most linear algebra routines, such as GEMM, SYRK and matrix transposition. We compare a broadcast bus based architecture with conventional SIMD, 2D-SIMD and flat register file for these operations in terms of area and energy efficiency. Results show that fast broadcast data movement abilities in a prototypical linear algebra core can achieve up to 75x better power and up to 10x better area efficiency compared to traditional SIMD architectures.

show abstract

The Potential Energy Efficiency of Vector Acceleration

Cited by 15 publications

References 15 publications

An Integrated Vector-Scalar Design on an In-Order ARM Core

An Integrated Vector-Scalar Design on an In-Order ARM Core

Algorithm/Architecture Codesign of Low Power and High Performance Linear Algebra Compute Fabrics

On the Efficiency of Register File versus Broadcast Interconnect for Collective Communications in Data-Parallel Hardware Accelerators

Contact Info

Product

Resources

About