The PHOTOBUS smart pixel interconnection system for symmetric multiprocessing using workstation clusters

IEEE Trans. Parallel Distrib. Syst.

2004

Abstract-In Symmetric Multiprocessors (SMPs), the cache coherence overhead and the speed of the shared buses limit the address/ snoop bandwidth needed to broadcast transactions to all processors. As a solution, a scalable address subnetwork called Symmetric Multiprocessor Network (SYMNET) is proposed in which address requests and snoop responses of SMPs are implemented optically. SYMNET not only uses passive optical interconnects that increases the speed of the proposed network, but also pipelines address requests at a much faster rate than electronics. This increases the address bandwidth for snooping, but the preservation of cache coherence can no longer be maintained with the usual snooping protocols. A modified coherence protocol, Coherence in SYMNET (COSYM), is introduced to solve the coherence problem. COSYM was evaluated with a subset of Splash-2 benchmarks and compared with the electrical bus-based MOESI protocol. The simulation studies have shown a 5-66 percent improvement in execution time for COSYM as compared to MOESI for various applications. Simulations have also shown that the average latency for a transaction to complete using COSYM protocol was 5-78 percent better than the MOESI protocol. It is also seen that SYMNET can scale up to hundreds of processors while still using fast snooping-based cache coherence protocols, and additional performance gains may be attained with further improvement in optical device technology.

Section: Related Workmentioning

confidence: 99%

An optical interconnection network and a modified snooping protocol for the design of large-scale symmetric multiprocessors (SMPs)

IEEE Trans. Parallel Distrib. Syst.

2004

“…The photobus smart pixel interconnection system for shared-memory multiprocessors uses optical buses for broadcasting the address requests, but arbitration is implemented with electronic buses leading to the buffering of address requests at the smart-pixel VLSI chip. 20 The Berkeley cachecoherence protocol is used in the photobus architec-ture. 1 The constraints of access arbitration is eliminated in the U-bus 7 design for SMPs.…”

Section: Related Workmentioning

confidence: 99%

SYMNET: an optical interconnection network for scalable high-performance symmetric multiprocessors

2003

Appl. Opt.

We address the primary limitation of the bandwidth to satisfy the demands for address transactions in future cache-coherent symmetric multiprocessors (SMPs). It is widely known that the bus speed and the coherence overhead limit the snoop/address bandwidth needed to broadcast address transactions to all processors. As a solution, we propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of SMPs are implemented optically. SYMNET not only has the ability to pipeline address requests, but also multiple address requests from different processors can propagate through the address subnetwork simultaneously. This is in contrast with all electrical bus-based SMPs, where only a single request is broadcast on the physical address bus at any given point in time. The simultaneous propagation of multiple address requests in SYMNET increases the available address bandwidth and lowers the latency of the network, but the preservation of cache coherence can no longer be maintained with the usual fast snooping protocols. A modified snooping cache-coherence protocol, coherence in SYMNET (COSYM) is introduced to solve the coherence problem. We evaluated SYMNET with a subset of Splash-2 benchmarks and compared it with the electrical bus-based MOESI (modified, owned, exclusive, shared, invalid) protocol. Our simulation studies have shown a 5-66% improvement in execution time for COSYM as compared with MOESI for various applications. Simulations have also shown that the average latency for a transaction to complete by use of COSYM protocol was 5-78% better than the MOESI protocol. SYMNET can scale up to hundreds of processors while still using fast snooping-based cache-coherence protocols, and additional performance gains may be attained with further improvement in optical device technology.

“…Optical-bus-based multiprocessor systems using coincident pulse technique provided optical solutions to the problems of bus design in areas of data transfer, bus arbitration, and device addressing [12]. The photobus smart pixel interconnection system for shared-memory multiprocessors used optical buses for address requests and broadcasts, but arbitration was implemented using electronic buses leading to buffering of address requests at the smart pixel very large-scale integration (VLSI) chip [13]. The constraints of access arbitration are eliminated in the U-bus [3] design for SMPs, which extends the address bandwidth, but a new coherence protocol has to be designed to maintain consistency across the caches.…”

Section: Related Workmentioning

confidence: 99%

Parallel optical interconnection network for SMPs

2003

Frontiers in Optics

The authors address the primary limitation of bandwidth demands for address transaction in future cache coherent symmetric multiprocessors (SMPs). As a solution, the authors propose a scalable address subnetwork called symmetric multiprocessor network (SYMNET) in which address requests and snoop responses of shared memory multiprocessors are implemented optically. As the address phase of the transaction is linked to the address bandwidth, which is the major bottleneck in SMPs, they focus only on the address subnetwork in this paper. SYMNET has the capability to pipeline address requests from successive processors, which results in increasing the available address bandwidth and lowering the latency of the network. An optical token is implemented to achieve mutual exclusion to the shared channel. This enables collisionless broadcast of multiple address requests. The simultaneous insertion of multiple address requests into the address subnetwork complicates cache coherence. A modified coherence protocol, called COSYM, was introduced to solve the coherence problem. The authors evaluated SYMNET with a subset of Splash-2 benchmarks running from 4-32 processors. Their simulation studies have shown 10%-67% improvement in execution time for various applications. It is also shown that the average latency for a transaction to complete using COSYM was 85% better than the electrical case. An overview of the proposed optical implementation of SYMNET is presented along with the theoretical power budget and bit-error rate analysis. This analysis shows that SYMNET can scale up to hundreds of processors while still using fast snoopy-based cache coherence protocols and that additional performance gains may be attained with further improvement in optical device technology.