An optical interconnection network and a modified snooping protocol for the design of large-scale symmetric multiprocessors (SMPs)

Abstract

Abstract-In Symmetric Multiprocessors (SMPs), the cache coherence overhead and the speed of the shared buses limit the address/ snoop bandwidth needed to broadcast transactions to all processors. As a solution, a scalable address subnetwork called Symmetric Multiprocessor Network (SYMNET) is proposed in which address requests and snoop responses of SMPs are implemented optically. SYMNET not only uses passive optical interconnects that increases the speed of the proposed network, but also pipelines address requests at a much faster rate than electronics. This increases the address bandwidth for snooping, but the preservation of cache coherence can no longer be maintained with the usual snooping protocols. A modified coherence protocol, Coherence in SYMNET (COSYM), is introduced to solve the coherence problem. COSYM was evaluated with a subset of Splash-2 benchmarks and compared with the electrical bus-based MOESI protocol. The simulation studies have shown a 5-66 percent improvement in execution time for COSYM as compared to MOESI for various applications. Simulations have also shown that the average latency for a transaction to complete using COSYM protocol was 5-78 percent better than the MOESI protocol. It is also seen that SYMNET can scale up to hundreds of processors while still using fast snooping-based cache coherence protocols, and additional performance gains may be attained with further improvement in optical device technology.

Leveraging Optical Technology in Future Bus-based Chip Multiprocessors

“…We comment on some recent efforts. Louri et al [36,37] propose snoopy address sub-interconnects where an optical token circulates around the processors to provide arbitration to transmit the requests through an H-tree like fully optical interconnect. This approach requires modification of the coherence protocol.…”

An Intelligent Supervising System for the Operation of an Underground Mine

“…Memory-tocache transfer occurs when the only clean copy is in the main memory. A cache block is written back (WB) in the main memory (bus is used) when a dirty copy is evicted [6]. The bus and the main memory are also used when synchronization procedures are executed [2].…”

Efficient techniques to provide scalability for token-based cache coherence protocols.

“…Systems can also use multiple addressinterleaved buses [32] and separate address and data subnetworks to multiply available bandwidth [32]. Even more aggressive systems avoid the electrical limitations of shared-wire buses entirely and implement a virtual bus using point-to-point links, dedicated switch chips, and distributed arbitration [32] or, even, use optical interconnection networks [72]. Asynchronous caches [98] are implemented by using a deeply pipelined memory system with parallellink interconnection and queues through which the memory and the processors communicate.…”