Although silicon optical technology is still in its formative stages, and the more near-term application is chip-to-chip communication, rapid advances have been made in the development of on-chip optical interconnects. In this paper, we investigate the integration of CMOS-compatible optical technology to on-chip cache-coherent buses in future CMPs.While not exhaustive, our investigation yields a hierarchical opto-electrical system that exploits the advantages of optical technology while abiding by projected limitations. Our evaluation shows that, for the applications considered, compared to an aggressive all-electrical bus of similar power and area, significant performance improvements can be achieved using an opto-electrical bus. This performance improvement is largely dependent on the application's bandwidth demand and on the number of implemented wavelengths per optical waveguide. We also present a number of critical areas for future work that we discover in the course of our research.
OPTICAL TECHNOLOGY OVERVIEWIn this work we consider on-chip modulator-based optical transmission (Figure 1), which comprises three major components: a transmitter, a waveguide, and a receiver. We briefly describe each component, and discuss technology trends in order to estimate the specifications of future designs. We propose one such design later in Section 3.
TransmitterOptical transmission requires a laser source, a modulator, and a modulator driver (electrical) circuit. The laser source provides light to the modulator, which transduces electricalThe 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06) 0-7695-2732
We demonstrate high bit rate electro-optic modulation in a resonant micrometer-scale silicon modulator over an ambient temperature range of 15 K. We show that low bit error rates can be achieved by varying the bias current through the device to thermally counteract the ambient temperature changes. Robustness in the presence of thermal variations can enable a wide variety of applications for dense on chip electronic photonic integration.
A method for canceling load-regulation, based on level shifting the reference, is proposed. In this architecture, the load current is monitored, sensed, and used to dynamically adapt the effective value of the reference voltage. The proposed architecture reduced a 2.5% load-regulation droop to a mere 0.2%, without compromising system stability. Introduction: Modern state-of-the-art technologies require higher accuracy performance from voltage regulators. With load-regulation performance being a significant factor, special attention is warranted in reducing its negative effects. In typical low drop-out (LDO) topologies, dc open-loop gain is severely restricted because of stringent stability
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