The performance of cache-coherent ring-based multiprocessors

Barroso, Luiz André; Dubois, Michel

doi:10.1145/165123.165162

Cited by 24 publications

References 30 publications

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Comparative performance evaluation of hot spot contention between MIN-based and ring-based shared-memory architectures

Zhang

Yan

Castaneda

1995

IEEE Trans. Parallel Distrib. Syst.

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Hot spot contention on a network-based sharedmemory architecture occurs when a large number of processors try to access a globally shared variable across the network. While Multistage Interconnection Network WIN) and HierarchicalRing (HR) structures are two important bases on which to build large scale shared-memory multiprocessors, the different interconnection networks and cachdmemory system of the two architectures respond very differently to network bottleneck situations. In this paper, we present a comparative performance evaluation of hot spot effects on the MIN-based and HR-based sharedmemory architectures. Both nonblocking MIN-based and HRbased architectures are classified, and analytical models are described for understanding network differences and for evaluating hot spot performance on both architectures. The analytical comparisons indicate that HR-based architectures have the potential to handle various contentions caused by hot spots more efficiently than MIN-based architectures. Intensive performance measurements on hot spots have been conducted on the BBN TC2000 (MIN-based) and the KSRl (HR-based) machines. Performance experiments were also conducted on the practical experience of hot spots with respect to synchronization lock algorithm. The experimental results are consistent with the analytical models, and present practical observations and an evaluation of hot spots on the two types of architectures.

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Comparative performance evaluation of hot spot contention between MIN-based and ring-based shared-memory architectures

Zhang

Yan

Castaneda

1995

IEEE Trans. Parallel Distrib. Syst.

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Comparative modeling and evaluation of CC-NUMA and COMA on hierarchical ring architectures

Zhang

Yan

1995

IEEE Trans. Parallel Distrib. Syst.

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Parallel computing performance on scaIable sharedmemory architectures is affected by the structure of the interconnection networks linking processors to memory modules and on the efficiency of the memorykache management systems. Cache Coherence Nonuniform Memory Access (CC-NUMA) and Cache Only Memory Access (COMA) are two effective memory systems, and the hierarchical ring structure is an effkient interconnection network in hardware. This paper focuses on comparative performance modeling and evaluation of CC-NUMA and COMA on a hierarchical ring shared-memory architecture. Analytical dels for the two memory systems for comparative evaluation are presented. Intensive performance measurements on data migrations have been conducted on the KSR-1, a COMA hierarchical ring shared-memory machine. Experimental results support the analytical models, and we present practical observations and compacisons of the two cache coherence memory systems. Our analytical and experimental results show that a COMA system balances the work load well. However the overhead of frequent data movement may match the gains obtained,from improving load balance. We believe our performance results could be further generalized to the two memory systems on a hierarchical network architecture. Although a CC-NUMA system may not automatically balance the load at the system level, it provides an option for a user to explicitly handle data locality for a possible performance improvement.

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SRC-based Cache Coherence Protocol in Chip Multiprocessor

Wang

2006

2006 Japan-China Joint Workshop on Frontier of Computer Science and Technology

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How to improve the scalability of snooping protocol and reduce the memory access latency of directorybased protocol are critical problems for performance optimization of multiprocessor systems. In this paper, we present an SRC (Sharing Relation Cache)-based protocol for chip multiprocessor architecture, in which protocol SRC is used to cache recently appeared sharing relations in case reuse in the near future. A two-phase write scheme is introduced to allow SRCbased protocol applicable not only in in-order network but also out-order network topology. By making full use of the temporal locality of sharing relations among processors, SRC-based protocol can heavily reduce the message traffic in CMP cache coherence protocols compared with snooping protocol. At the same time, SRC-based protocol has better memory access latency than directory-based protocol.

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The performance of cache-coherent ring-based multiprocessors

Cited by 24 publications

References 30 publications

Comparative performance evaluation of hot spot contention between MIN-based and ring-based shared-memory architectures

Comparative performance evaluation of hot spot contention between MIN-based and ring-based shared-memory architectures

Comparative modeling and evaluation of CC-NUMA and COMA on hierarchical ring architectures

SRC-based Cache Coherence Protocol in Chip Multiprocessor

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