SRC-based Cache Coherence Protocol in Chip Multiprocessor

Abstract

How to improve the scalability of snooping protocol and reduce the memory access latency of directorybased protocol are critical problems for performance optimization of multiprocessor systems. In this paper, we present an SRC (Sharing Relation Cache)-based protocol for chip multiprocessor architecture, in which protocol SRC is used to cache recently appeared sharing relations in case reuse in the near future. A two-phase write scheme is introduced to allow SRCbased protocol applicable not only in in-order network but also out-order network topology. By making full use of the temporal locality of sharing relations among processors, SRC-based protocol can heavily reduce the message traffic in CMP cache coherence protocols compared with snooping protocol. At the same time, SRC-based protocol has better memory access latency than directory-based protocol.

Exploit Temporal Locality of Shared Data in SRC Enabled CMP

“…We proposed an efficient technique to reduce network traffic of broadcastbased protocol, which was called sharing relation cache (SRC) [10]. The idea came from the following characteristic that we found in the run-time characteristic analysis of parallel workloads: a majority of shared data accesses has temporal locality.…”