The performance and energy consumption of three embedded real-time operating systems

Baynes, K.; Collins, Chris; Fiterman, Eric; Ganesh, Brinda; Kohout, Paul; Smit, Christine; Zhang, Tiebing; Jacob, Bruce

doi:10.1145/502251.502253

Cited by 6 publications

(6 citation statements)

References 15 publications

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“…Our experimental setup for estimating the energy consumption of programs with and without our method is as follows. An M-core power simulator [14,15], kindly donated by that group, is used to obtain energy estimates for instructions and SRAM. This is an instruction-level power simulator similar to [71,82]; its instruction power numbers were measured using an ammeter connected to an M-core hardware board.…”

Section: Resultsmentioning

confidence: 99%

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Udayakumaran

Barua

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

141

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In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardwaremanaged cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in energy consumption, area and overall runtime, even with a simple allocation scheme. Scratch-pad allocation methods primarily are of two types. First, softwarecaching schemes emulate the workings of a hardware cache in software. Instructions are inserted before each load/store to check the software-maintained cache tags.Such methods incur large overheads in runtime, code size, energy consumption and SRAM space for tags and deliver poor real-time guarantees, just like hardware caches. A second category of algorithms partitions variables at compile-time into the two banks. However, a drawback of such static allocation schemes is that they do not account for dynamic program behavior.We propose a dynamic allocation methodology for global and stack data and program code that (i) accounts for changing program requirements at runtime (ii) has no software-caching tags (iii) requires no run-time checks (iv) has extremely low overheads, and (v) yields 100% predictable memory access times. In this method data that is about to be accessed frequently is copied into the scratch-pad using compiler-inserted code at fixed and infrequent points in the program. Earlier data is evicted if necessary. When compared to an existing static allocation scheme, results show that our scheme reduces runtime by up to 39.8% and energy by up to 31.3% on average for our benchmarks, depending on the SRAM size used. The actual gain depends on the SRAM size, but our results show that close to the maximum benefit in run-time and energy is achieved for a substantial range of small SRAM sizes commonly found in embedded systems. Our comparison with a direct mapped cache shows that our method performs roughly as well as a cached architecture in runtime and energy while delivering better real-time benefits. Albert SchweitzerWith these thoughts in mind, I embark on this humble duty to acknowledge different people who have contributed to that light in their own ways.First and foremost, I acknowledge my parents, my brother and my sister-inlaw whose concern for my health and wellbeing, always drives me to work harder towards my goals.I would also like to acknowledge those who have helped me to complete this dissertation. My advisor, Dr. Rajeev Barua, has been an outstanding motivator.

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Section: Resultsmentioning

confidence: 99%

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Udayakumaran

Barua

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

141

View full text Add to dashboard Cite

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“…An M-core power simulator [Baynes et al 2001;2003], kindly donated by that group, is used to obtain energy estimates for instructions and SRAM. This is an instruction-level power simulator similar to [Sinha and Chandrakasan 2001;Tiwari and Lee 1998]; its instruction power numbers were measured using an ammeter connected to an M-core hardware board.…”

Section: Methodsmentioning

confidence: 99%

Dynamic allocation for scratch-pad memory using compile-time decisions

Udayakumaran

Domínguez

Barua

2006

ACM Trans. Embed. Comput. Syst.

183

156

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In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in energy consumption, area and overall runtime, even with a simple allocation scheme.Scratch-pad allocation primarily methods are of two types. First, software-caching schemes emulate the workings of a hardware cache in software. Instructions are inserted before each load/store to check the softwaremaintained cache tags. Such methods incur large overheads in runtime, code size, energy consumption and SRAM space for tags and deliver poor real-time guarantees just like hardware caches. A second category of algorithms partitions variables at compile-time into the two banks. However, a drawback of such static allocation schemes is that they do not account for dynamic program behavior. It is easy to see why a data allocation that never changes at runtime cannot achieve the full locality benefits of a cache.We propose a dynamic allocation methodology for global and stack data and program code that, (i) accounts for changing program requirements at runtime (ii) has no software-caching tags (iii) requires no run-time checks (iv) has extremely low overheads, and (v) yields 100% predictable memory access times. In this method data that is about to be accessed frequently is copied into the scratch-pad using compiler-inserted code at fixed and infrequent points in the program. Earlier data is evicted if necessary. When compared to a provably optimal static allocation, results show that our scheme reduces runtime by up to 39.8% and energy by up to 31.3% on average for our benchmarks, depending on the SRAM size used. The actual gain depends on the SRAM size, but our results show that close to the maximum benefit in run-time and energy is achieved for a substantial range of small SRAM sizes commonly found in embedded systems. Our comparison with a direct mapped cache shows that our method performs roughly as well as a cached architecture.

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“…We also study the effect of using the doze instruction on the energy consumption of the RTOS. More detail on the MCORE processor, SimBed's internals, applications, and RTOS models can be found elsewhere [4], [5], [8], [44].…”

Section: Characterization Of Real-time Behaviormentioning

confidence: 99%

The performance and energy consumption of embedded real-time operating systems

Baynes

Collins

Fiterman³

et al. 2003

IEEE Trans. Comput.

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Abstract-This paper presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs by executing them on an accurate architectural model of a microcontroller with simulated real-time stimuli. We briefly describe the simulation environment and present a study that compares three RTOSs: C/OS-II, a popular public-domain embedded real-time operating system; Echidna, a sophisticated, industrial-strength (commercial) RTOS; and NOS, a bare-bones multirate task scheduler reminiscent of typical "roll-your-own" RTOSs found in many commercial embedded systems. The microcontroller simulated in this study is the Motorola M-CORE processor: a low-power, 32-bit CPU core with 16-bit instructions, running at 20MHz. Our simulations show what happens when RTOSs are pushed beyond their limits and they depict situations in which unexpected interrupts or unaccounted-for task invocations disrupt timing, even when the CPU is lightly loaded. In general, there appears no clear winner in timing accuracy between preemptive systems and cooperative systems. The power-consumption measurements show that RTOS overhead is a factor of two to four higher than it needs to be, compared to the energy consumption of the minimal scheduler. In addition, poorly designed idle loops can cause the system to double its energy consumption-energy that could be saved by a simple hardware sleep mechanism.

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The performance and energy consumption of three embedded real-time operating systems

Cited by 6 publications

References 15 publications

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Dynamic allocation for scratch-pad memory using compile-time decisions

The performance and energy consumption of embedded real-time operating systems

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