The optimization of deep trench isolation structure for high voltage devices on SOI substrate

Qian, Qinsong; Sun, Weifeng; Han, Dianxiang; Liu, Siyang; Su, Zhan; Shi, Longxing

doi:10.1016/j.sse.2011.05.020

Cited by 5 publications

(5 citation statements)

References 9 publications

(12 reference statements)

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“…4 Anisotropy of the dry etch process can be achieved and is useful for mesa definition. 5 Anisotropic dry etching is used in device isolation, 6 in modern DRAM capacitor, 7 and in power device fabrication. 8 Reactive ion etching (RIE) is most commonly used during semiconductor device fabrication as it allows both physical and plasma etching simultaneously.…”

Section: Introductionmentioning

confidence: 99%

“…The results of Syau et al showed that the etch rate of Si declined as O 2 content was increased and found that the anisotropy depended on the substrate temperature when using 25% of O 2 in SF 6 -O 2 gas mixture. Another important work is Campo et al 13 concerned with how O 2 content (%O 2 ) in SF 6 -O 2 gas mixtures affected Si and Ge dry etching. They found that Si has some selectivity and up to 2Â different etch rates with respect to Ge, with O 2 content below 50%.…”

Section: Introductionmentioning

confidence: 99%

“…14 made comparable studies on Si using SF 6 -O 2 -CHF 3 gas mixtures, the addition of CHF 3 was used to reduce the surface roughness of the etched surface. Zou 15 also found the anisotropy in Si etching depended on the O 2 content and total pressure.…”

Section: Introductionmentioning

confidence: 99%

“…They found that gas flow, power and total pressure influenced both the etch rate and anisotropy. Recent work in 2013 by Liu et al 17 considered SF 6 -O 2 plasma etching on silicon at low temperatures. When the temperature was decreased, the etching indicated more anisotropy.…”

Section: Introductionmentioning

confidence: 99%

“…We also investigate how the %O 2 in the SF 6 -O 2 gas mixture influences the side wall orientation and profile for the room temperature SF 6 -O 2 dry etching. We use Si as the control.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Precision plasma etching of Si, Ge, and Ge:P by SF6 with added O2

Wongwanitwattana¹,

Shah²,

Myronov³

et al. 2014

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

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The impact of the O 2 content in SF 6 -O 2 gas mixtures on the etch rate and sidewall profile of silicon (Si), germanium (Ge), and phosphorous doped germanium (Ge:P) in reactive ion etching has been studied. The characteristics of etch rate and sidewall profile are greatly affected by the O 2 content. Below 50% of O 2 content, a large variation in Ge etch rates is found compared to that of Si, but for O 2 content above 50% the etch rates follow relatively the same trend. Lightly doped Ge shows the highest etch rate at a O 2 concentration up to 20%. Sidewall angles range from a minimum of 80 to a maximum of 166 , with O 2 concentration of 20% yielding perfect anisotropic mesa etch. Also at this O 2 concentration, reasonable Si/Ge selectivity is possible. These observations indicate that by adjusting the O 2 concentration, precision plasma etching of Si, Ge, and Ge:P is possible.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

“…We also investigate how the %O 2 in the SF 6 -O 2 gas mixture influences the side wall orientation and profile for the room temperature SF 6 -O 2 dry etching. We use Si as the control.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Precision plasma etching of Si, Ge, and Ge:P by SF6 with added O2

Wongwanitwattana¹,

Shah²,

Myronov³

et al. 2014

Journal of Vacuum Science &Amp; Technology A: Vacuum, Surfaces, and Films

View full text Add to dashboard Cite

show abstract

Novel 700 V high-voltage SOI LDMOS structure with folded drift region

Jianghui

et al. 2015

J. Semicond.

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A new high-voltage LDMOS with folded drift region (FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.

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Thin silicon layer SOI power device with linearly-distance fixed charge islands

Zuo

Jianghui

et al. 2015

J. Semicond.

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A new high-voltage LDMOS with linearly-distanced fixed charge islands is proposed (LFI LDMOS). A lot of linearly-distanced fixed charge islands are introduced by implanting the Cs or I ion into the buried oxide layer and dynamic holes are attracted and accumulated, which is crucial to enhance the electric field of the buried oxide and the vertical breakdown voltage. The surface electric field is improved by increasing the distance between two adjacent fixed charge islands from source to drain, which lead to the higher concentration of the drift region and a lower on-resistance. The numerical results indicate that the breakdown voltage of 500 V with Ld = 45 μm is obtained in the proposed device in comparison to 209 V of conventional LDMOS, while maintaining low on-resistance.

show abstract

The optimization of deep trench isolation structure for high voltage devices on SOI substrate

Cited by 5 publications

References 9 publications

Precision plasma etching of Si, Ge, and Ge:P by SF6 with added O2

Precision plasma etching of Si, Ge, and Ge:P by SF6 with added O2

Novel 700 V high-voltage SOI LDMOS structure with folded drift region

Thin silicon layer SOI power device with linearly-distance fixed charge islands

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