The Operation Algorithm for Improving the Reliability of TLC (Triple Level Cell) NAND Flash Characteristics

Lee, Dong Hoon; Cho, Sunghoon; Kang, Byung Woo; Park, Sukkwang; Park, Byoung-Jun; Cho, Myoung Kwan; Ahn, Kun-Ok; Yang, Y.; Park, Sung Wook

doi:10.1109/imw.2011.5873234

Cited by 6 publications

(3 citation statements)

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“…1. Here, we should note that in TLC NAND Flash, Gray-code has been used for the mapping between each state and page information [5]. For example, '110' (the 1 st page: 0, the 2 nd and the 3 rd pages: 1) is mapped to P 7 -state while P 6 -state represents '010' (the 1 st and the 3 rd pages: 0, the 2 nd page: 1).…”

Section: State Re-orderingmentioning

confidence: 99%

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Bit-error rate improvement of TLC NAND Flash using state re-ordering

Chang

Yang

2012

IEICE Electron. Express

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In scaled technologies, large cell-to-cell interference and F-N tunneling disturbance degrade threshold voltage (V t ) window which we can place program states. Moreover, in Triple Layer Cell (TLC) NAND Flash we should place seven program states (P 1~P7 ) in the narrow V t window, incurring large biterror rate (BER). In this paper, we propose a state re-ordering technique to increase the efficiency of V t window utilization in TLC NAND Flash memories. Our simulation results show that under equivalent V t window sizes, the proposed technique provides 12.5~18.4% smaller BER compared to conventional Gray-code mapping.

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Section: State Re-orderingmentioning

confidence: 99%

“…As shown in Fig. 2, four RL's (RL 1 , RL 3 , RL 5 , and RL 7 ) are necessary for the 3 rd pages reading due to Gray-code mapping. Under the assumption that the MCN is 40-bits, the average number of bit-errors per each RL in the 3 rd page reading is 10-bits.…”

Section: State Re-orderingmentioning

confidence: 99%

Bit-error rate improvement of TLC NAND Flash using state re-ordering

Chang

Yang

2012

IEICE Electron. Express

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“…The Multi-Level Cell technology currently being used by memory manufacturers to increase the degree of integration is accompanied by some adverse effects that deteriorate important characteristics of memory chips such as program time, longevity and reliability. MLC or TLC (Triple-Level Cell) flash memories which are frequently used in large capacity SSDs show lower speed, shorter lifespans, and higher bit error rates compared to SLC flash memories [9,19,16]. To prevent these problems that appear at the chip level from being exposed at the device level, gradually more complicated hardware and software technologies cannot but be used in SSDs.…”

Section: Introductionmentioning

confidence: 99%

Dual region write buffering

Kim

Kang

2015

Proceedings of the 30th Annual ACM Symposium on Applied Computing

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Write buffering not only enables Solid State Drive (SSD) to immediately respond to the write request but also increases the lifespan of the SSD by reducing the amount of data written to the flash memory. However, since the DRAM which is used as a write buffer is volatile, it has a few critical problems such as buffered data loss upon sudden power-off and limited write reduction effect due to the flush commands and synchronous writes from the file system. These problems can be addressed when non-volatile memory (NVRAM) is used, instead of DRAM, as a write buffer. In this paper, we propose a novel Dual-Region Write Buffering (DRWB) scheme that implements logically non-volatile write buffer using large sized DRAM and small capacity capacitor. The DRWB exploits the differential write scheme, which has been developed originally for the write reduction in SSD, to protect data in the write buffer. Experimental results show that the proposed scheme enables us to achieve the same effect with the NVRAM write buffer, in terms of the data reliability, without noticeable performance degradation.

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