The model of solid phase crystallization of amorphous silicon under elastic stress

Kimura, Yasuo; Kishi, Masato; Katoda, Takashi

doi:10.1063/1.372448

Cited by 12 publications

(7 citation statements)

References 12 publications

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“…However, with SMT processing using LT-SiN, the wafer bow is increased further after S/D activation annealing due to the large increase in film stress reported in Table II. Recrystallization of amorphized silicon upon thermal annealing leads to strain and stress generation in the silicon material itself. [19][20][21][22] Because the transistor's poly-silicon gate and the S/D region were all amorphorized after high dosage S/D implantation, this increased tensile wafer curvature after annealing is likely to result from the SMT capping nitride film stress change and the strain exerted by the recrystallization of the amorphized S/D regions upon S/D activation annealing. Nevertheless, wafer warpage continues to exist even after the SMT nitride is subsequently removed, both for wafers processed with SMT by LT-SiN and for those with HT-SiN.…”

Section: H706mentioning

confidence: 97%

Characterization of Highly Strained nFET Device Performance and Channel Mobility with SMT

Huang

Luo

et al. 2010

J. Electrochem. Soc.

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This paper compares and analyzes the strained negative channel field effect transistor ͑nFET͒ device performance and the channel mobility behavior obtained by the stress memorization technique ͑SMT͒ using two different types of nitride films. These nitride film properties and wafer bowing during SMT fabrication are investigated. The electrical properties of SMT strained nFET devices including current-voltage characteristics, transconductance, carrier mobility, and interface state ͑D it ͒ are also analyzed. Although SMT nitride strain can enhance electron mobility, it is critical to control the nitride properties and its hydrogen content to minimize electron mobility degradation due to interface-state generation. Thus, a simple view of the essential physics of mobility enhancement in SMT strained nFETs has been provided. Results in this work also provide guidance to further nFET performance enhancement in the ever-more challenging device targets of future technology generations.Historically, improvements in the performance of metal-oxidesemiconductor field-effect transistors ͑MOSFETs͒ have relied on the aggressive reduction of physical geometries as guided by physicsbased scaling rules. 1 However, the increase in channel impurity concentration and the raise in vertical field required to control the short channel effect ͑SCE͒ actually degrade the carrier mobility and transistor performance. As the industry approaches the physical limitations of the traditional scaling techniques, alternative approaches for improving device performance have become increasingly attractive. Among the most promising of these techniques is the production of high mobility silicon channel structures most commonly accomplished using strained silicon technology. Strained silicon technology has emerged as one of the leading approaches to enhance the performance of today's highly scaled semiconductor devices. This technology has been adopted in production since the 90 nm process node, 2 and apparently this technology will continue through future generations. The strain can be induced either uniaxially or biaxially and strongly depends on integration challenges and the ability to maintain and control enhancement in aggressively scaled devices.Many strained silicon approaches have thus been developed to enhance carrier mobility. 2-4 Among these emerging approaches, uniaxial strained silicon technologies have become the mainstream for electron and hole mobility improvement especially under high oxide electrical field conditions. 3,4 For instance, a highly tensile nitride capping layer integrated as a contact etch stop layer ͑CESL͒ has been greatly utilized in advanced MOSFET fabrication owing to the resulting uniaxially tensile mechanical stress created in the negative channel field effect transistor ͑nFET͒ channel and the resulting electron mobility enhancement. 5,6 Another novel channel strain enhancement technique utilizing nitride dielectric deposition, commonly known as stress memorization technique ͑SMT͒, was first proposed by Chen et al. ...

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Section: H706mentioning

confidence: 97%

Characterization of Highly Strained nFET Device Performance and Channel Mobility with SMT

Huang

Luo

et al. 2010

J. Electrochem. Soc.

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“…Our results show the enhancement of crystallization when under compressive stress and reduced crystallization in tensile strained samples. Kimura [38] used a model to discuss the effect of stress on crystallization of a-Si. Based on this model the driving energy of crystallization is the difference in Helmholtz energy between c-Si and a-Si under stress.…”

Section: Stress Evolution Of Ge Ncs In Superlattices With Buffer Layersmentioning

confidence: 99%

Stress evolution of Ge nanocrystals in dielectric matrices

Bahariqushchi¹,

Raciti²,

Kasapoğlu³

et al. 2018

Nanotechnology

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Germanium nanocrystals (Ge NCs) embedded in single and multilayer silicon oxide and silicon nitride matrices have been synthesized using plasma enhanced chemical vapor deposition followed by conventional furnace annealing or rapid thermal processing in N ambient. Compositions of the films were determined by Rutherford backscattering spectrometry and x-ray photoelectron spectroscopy. The formation of NCs under suitable process conditions was observed with high resolution transmission electron microscope micrographs and Raman spectroscopy. Stress measurements were done using Raman shifts of the Ge optical phonon line at 300.7 cm. The effect of the embedding matrix and annealing methods on Ge NC formation were investigated. In addition to Ge NCs in single layer samples, the stress on Ge NCs in multilayer samples was also analyzed. Multilayers of Ge NCs in a silicon nitride matrix separated by dielectric buffer layers to control the size and density of NCs were fabricated. Multilayers consisted of SiN :Ge ultrathin films sandwiched between either SiO or SiN by the proper choice of buffer material. We demonstrated that it is possible to tune the stress state of Ge NCs from compressive to tensile, a desirable property for optoelectronic applications. We also observed that there is a correlation between the stress and the crystallization threshold in which the compressive stress enhances the crystallization, while the tensile stress suppresses the process.

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“…14 On the other hand, there are some reports on the suppressing effect of the interfacial stress on the rate of crystallization and that nucleation starts at the surface of the a-Si rather than the interface, when a biaxial stress is induced from a fused silica substrate 15 or from an overlayer such as a Si 3 N 4 cap. 16 In the case of MIC, while the basic mechanism is still a subject of study, it has been claimed that compressive stress and lattice shrinkage caused by the introduced metal is the principal factor in Al-induced crystallization of a-Ge. 17 We have speculated that such internal stresses may be reinforced by external mechanical stress to become more effective.…”

Section: Introductionmentioning

confidence: 99%

High mobility poly-Ge thin-film transistors fabricated on flexible plastic substrates at temperatures below 130°C

Shahrjerdi

Hekmatshoar

Mohajerzadeh

et al. 2004

Journal of Elec Materi

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Depletion-mode poly-Ge thin-film transistors (TFTs) with an effective hole mobility of 110 cm 2 /Vs and an ON/OFF ratio of 10 4 have been fabricated on flexible polyethylene therephtalate (PET) substrates, taking advantage of a novel stress-assisted crystallization technique. Proper manipulation of an otherwise destructive mechanical stress leads to a drastic drop of crystallization temperature from 400°C to 130°C. External compressive stress is transferred to the Ge/PET interface by bending the flexible substrate inward, during the thermal post-treatment. Proper patterning of the a-Ge layer before thermomechanical post-treatment leads to a minimal crack density in the processed poly-Ge layer. Reduction in the crack density plays a crucial role in alleviating the stress-induced gate leakage current emanated from the crack traces propagating from the channel into the gate oxide.

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The model of solid phase crystallization of amorphous silicon under elastic stress

Cited by 12 publications

References 12 publications

Characterization of Highly Strained nFET Device Performance and Channel Mobility with SMT

Characterization of Highly Strained nFET Device Performance and Channel Mobility with SMT

Stress evolution of Ge nanocrystals in dielectric matrices

High mobility poly-Ge thin-film transistors fabricated on flexible plastic substrates at temperatures below 130°C

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