The micro to nano addressing block (MNAB)

Gopalakrishnan, Kailash; Shenoy, Rohit S.; Rettner, C. T.; King, R. S.; Zhang, Y.; Kurdi, B. N.; Bozano, Luisa; Welser, J.J.; Rothwell, Mary Beth; Jurich, M.; Sanchez, Martha I.; Hernández, Mauricio A.; Rice, Phil; Risk, W. P.; Wickramasinghe, H. K.

doi:10.1109/iedm.2005.1609382

Cited by 12 publications

(8 citation statements)

References 4 publications

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“…In the periphery of such regular arrays of memory devices are CMOS logic circuits that allow controlled access to the memory cells for programming and reading the data stored in them. It is also worth mentioning that there are other exciting fabrication ideas that are pursued such as three-dimensional integration [162] and sub-lithographic cross-bar arrays [50] to enhance memory capacity beyond what is possible by conventional methods. Further, it is also typical to provide extra memory devices and associated decoding circuitry on each word-line for redundancy and error correction.…”

Section: Next Generation Memory Technologies -mentioning

confidence: 99%

Phase Change Memory: From Devices to Systems

Qureshi

Gurumurthi

Rajendran³

2011

Synthesis Lectures on Computer Architecture

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Section: Next Generation Memory Technologies -mentioning

confidence: 99%

Phase Change Memory: From Devices to Systems

Qureshi

Gurumurthi

Rajendran³

2011

Synthesis Lectures on Computer Architecture

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“…We have already extensively discussed one of these, that is, multiple bits per cell using MLC techniques in Sec-tion V A. Two other approaches that have been discussed are the implementation of a sublithographic crossbar memory to go beyond the lithographic dimension, F [244,245], and 3-D integration of multiple layers of memory, currently implemented commercially for writeonce solid-state memory [246].…”

Section: Routes To Ultra-high Densitymentioning

confidence: 99%

Phase change memory technology

Burr,

Breitwisch,

Franceschini

et al. 2010

Preprint

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We survey the current state of phase change memory (PCM), a non-volatile solid-state memory technology built around the large electrical contrast between the highly-resistive amorphous and highly-conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance and yield characteristics.We introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. We then address challenges for the technology, including the design of PCM cells for low RESET current, the need to control device-to-device variability, and undesirable changes in the phase change material that can be induced by the fabrication procedure. We then turn to issues related to operation of PCM devices, including retention, device-to-device thermal crosstalk, endurance, and bias-polarity effects. Several factors that can be expected to enhance PCM in the future are addressed, including Multi-Level Cell technology for PCM (which offers higher density through the use of intermediate resistance states), the role of coding, and possible routes to an ultra-high density PCM technology.

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“…This allows a bit of data to be written by altering the physical state of the nanowires' point(s) of intersection (see Figure 1). A range of technologies have been presented to realize decoders for memories including using masks [1], [2], axial NW encoding [3], [4], radial NW encoding [5], random particle deposition [6], rotational offsets of intersecting sets of wires [7], [8], and micro-to-nano addressing blocks [9].…”

Section: Introductionmentioning

confidence: 99%

Stochastic nanoscale addressing for logic

Rachlin¹,

Savage²

2010

2010 IEEE/ACM International Symposium on Nanoscale Architectures

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Abstract-In this paper we explore the area overhead associated with the stochastic assembly of nanoscale logic. In nanoscale architectures, stochastically assembled nanowire decoders have been proposed as a way of addressing many individual nanowires using as few photolithographically produced mesoscale wires as possible. Previous work has bounded the area of stochastically assembled nanowire decoders for controlling nanowire crossbarbased memories. We extend this analysis to nanowire crossbarbased logic and bound the area required to supply inputs to a nanoscale circuit via mesoscale wires. We also relate our analysis to the area required for stochastically assembled signalrestoration layers within nanowire crossbar-based logic.

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The micro to nano addressing block (MNAB)

Cited by 12 publications

References 4 publications

Phase Change Memory: From Devices to Systems

Phase Change Memory: From Devices to Systems

Phase change memory technology

Stochastic nanoscale addressing for logic

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