The limitations in applying analytic design equations for optimal class E RF power amplifiers design

Lie, Donald Y. C.; Lee, P.; Popp, J.D.; Rowland, Jason; Ng, HK; Yang, A.T.

doi:10.1109/vdat.2005.1500045

Cited by 18 publications

(20 citation statements)

References 15 publications

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“…However, the "finite dc-feed inductance" and the "non-zero switch on-resistance" significantly influence the performance of the Class-E PAs [2]. To alleviate the analytical complexity, theoretical analyses of the Class-E PA in the literature assumed either non-zero switch-on resistance and infinite dc-feed inductance (RF-choke) [3]- [7] or zero switch-on resistance and finite dc-feed inductance [8]- [11].…”

Section: Introductionmentioning

confidence: 99%

“…In order to design Class-E PAs with optimum performance an improved analytical model that takes into account both the finite drain inductance and non-zero switch on-resistance is therefore needed [2].…”

Section: Introductionmentioning

confidence: 99%

“…1 The Class-E topology given in [21] assumes zero switch parallel capacitor; which is only applicable for very dedicated technologies with very small RonCout product, where Cout is the switch (transistor) output capacitance. 2 In [9] and [10], the switch on-resistance is assumed to be zero.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance

Acar

Annema

Nauta

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-Many critical design trade-offs of the Class-E power amplifier (e.g power efficiency) are influenced by the switch onresistance and the value of dc-feed drain inductance. In literature, the time-domain mathematical analyses of the Class-E power amplifier with finite dc-feed inductance assume zero switch onresistance in order to alleviate the mathematical difficulties; resulting in non-optimum designs.We present analytical design equations in this paper for Class-E power amplifier taking into account both finite drain inductance and switch on-resistance. The analysis indicates the existence of infinitely many design equations; conclusions include: 1) Class-E conditions (e.g. zero voltage and zero slope) can be satisfied in the presence of switch-on resistance.2) The drain-efficiency (η) of the Class-E power amplifier is upper limited for a certain operation frequency and transistor technology.3) Using a finite dc-feed inductance instead of an RF-choke in a Class-E power amplifier can increase η by ≈ 30%.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance

Acar

Annema

Nauta

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…As conventional RF choke inductor used in the DC bias circuit of the FEM needs high inductance values ('7e100 nH ranged at 300 MHz) [4] which might have inductance values of ϳ30 nH, or more at 1 GHz, it causes high cost and large size of the FEM. In addition, the large inductance causes voltage drop in the DC bias circuit resulting in the poor adjacent channel power ratio (ACPR) of the FEM.…”

Section: Introductionmentioning

confidence: 99%

“…However, to provide a complete radio function, the antenna also needs to be integrated into the radio-frequency SiP. For this kind of internal antenna design, a compact radiating patch is usually employed and stacked on the top above a small conducting plate as the antenna's ground plane and the shield for the underlying RF circuitry and modules [2][3][4]. This configuration in general leads to an increase in the overall height of the package and also results in narrow band operation.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and optimization of organic SIP based FEM for CDMA handset applications

Lee¹,

Cheon²,

Cho

et al. 2006

Microw. Opt. Technol. Lett.

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Design of highly-efficient wideband RF polar transmitters using the Envelope-Tracking technique

Lie

Lopez

2008

2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting

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This paper discusses the design issues of highly efficient and monolithic wideband RF polar transmitters, especially the ones that use the EnvelopeTracking (ET) technique. Besides reviewing the stateof-the-art polar transmitters in the literature, three focus topics will be discussed: (1) the system-on-achip (SoC) design considerations of the monolithic polar transmitter using ET; and (2) the design of highly-efficient envelope amplifier capable of achieving the high efficiency, current, bandwidth, accuracy and noise specifications required for wideband signals; and (3) the design of highefficiency monolithic Si-based power amplifiers (PAs) suitable for ET-based RF polar transmitters.

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The limitations in applying analytic design equations for optimal class E RF power amplifiers design

Cited by 18 publications

References 15 publications

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance

Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-Resistance

Fabrication and optimization of organic SIP based FEM for CDMA handset applications

Design of highly-efficient wideband RF polar transmitters using the Envelope-Tracking technique

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