The Latency-of-Data-Access model for analyzing parallel computation

Simon, Jens; Wierum, Jens-Michael

doi:10.1016/s0020-0190(98)00062-3

Cited by 2 publications

(3 citation statements)

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“…We have presented a generic execution-driven simulator for the accurate prediction of memory accesses based on the Latency-of-Data-Access Model [9]. This model is motivated by the observation that the computation speed of modern computers is dominated by the access time to the various memory levels.…”

Section: Resultsmentioning

confidence: 99%

“…The Latency-of-Data-Access (LDA) model [9] can be used to predict the execution characteristics of an application on a sequential or parallel architecture. It is based on the observation that the computation performance is dominated (and also strictly limited) by the speed of the memory system.…”

Section: The Latency-of-data-access Modelmentioning

confidence: 99%

“…In LDA, data movements are modeled by direct memory accesses to the various levels in the memory hierarchy. The number of data movements combined with the costs of computations provide an accurate estimate on the expected runtime [9].…”

Section: The Latency-of-data-access Modelmentioning

confidence: 99%

See 2 more Smart Citations

A Cache Simulator for Shared Memory Systems

Schintke¹,

Simon²,

Reinefeld³

2001

Computational Science - ICCS 2001

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Abstract. Due to the increasing gap between processor speed and memory access time, a large fraction of a program's execution time is spent in accesses to the various levels in the memory hierarchy. Hence, cacheaware programming is of prime importance. For efficiently utilizing the memory subsystem, many architecture-specific characteristics must be taken into account: cache size, replacement strategy, access latency, number of memory levels, etc. In this paper, we present a simulator for the accurate performance prediction of sequential and parallel programs on shared memory systems. It assists the programmer in locating the critical parts of the code that have the greatest impact on the overall performance. Our simulator is based on the Latency-of-Data-Access Model, that focuses on the modeling of the access times to different memory levels. We describe the design of our simulator, its configuration and its usage in an example application.

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Section: Resultsmentioning

confidence: 99%

Section: The Latency-of-data-access Modelmentioning

confidence: 99%