Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction

Min, Su Myat; Peddersen, Jorgen; Parameswaran, Sri

doi:10.1109/vlsid.2011.36

Cited by 4 publications

(2 citation statements)

References 9 publications

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“…We used the cycle-accurate simulator from [25] 1 and tool from [7] as processor-memory simulator and cache simulator in XDRA. In addition, CACTI 6.5 [22] was configured for a given 90nm technology to obtain energy consumption and area of L2 cache configurations.…”

Section: Experiments and Resultsmentioning

confidence: 99%

“…Accurate computation of DRAM's active time is not possible because DRAM accesses take differing cycles depending upon DRAM state [25], which is unknown unless cycle-accurate simulation is performed. Therefore, we estimate DRAM active time as [DRAM accesses × fixed DRAM access latency], where the fixed latency is an average of latencies of all DRAM accesses from cycle-accurate simulation performed during the 'LCI profile generation' step.…”

Section: Xdra Frameworkmentioning

confidence: 99%

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Xdra

Min

Javaid

Parameswaran

2013

Proceedings of the 50th Annual Design Automation Conference

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Embedded systems with high energy consumption often exploit the idleness of DDR-DRAM to reduce their energy consumption by putting the DRAM into deepest low-power mode (self-refresh power down mode) during idle periods. DDR-DRAM idle periods heavily depend on the last-level cache. Exhaustive search using processor-memory simulators can take several months. This paper for first time proposes a fast framework called XDRA, which allows the exploration of lastlevel cache configurations to improve DDR-DRAM energy efficiency.XDRA combines a processor-memory simulator, a cache simulator and novel analysis techniques to produce a Kriging based estimator which predicts the energy savings for differing cache configurations for a given main memory size and application. Errors for the estimator were less than 4.4% on average for 11 applications from mediabench and SPEC2000 suite and two DRAM sizes (Micron DDR3-DRAM 256MB and 4GB). Cache configurations selected by XDRA were on average 3.6× and 4× more energy efficient (cache and DRAM energy) than a common cache configuration. Optimal cache configurations were selected by XDRA 20 times out of 22. The two suboptimal configurations were at most 3.9% from their optimal counterparts. XDRA took a few days for the exploration of 330 cache configurations compared to several hundred days of cycle-accurate simulations, saving at least 85% of exploration time.

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Section: Experiments and Resultsmentioning

confidence: 99%

Section: Xdra Frameworkmentioning

confidence: 99%