The Key Role of Memory in Next-Generation Embedded Systems for Military Applications

Abstract

With the increasing use of multi-core platforms in safetyrelated domains, aircraft system integrators and authorities exhibit a concern about the impact of concurrent access to shared-resources in the Worst-Case Execution Time (WCET). This paper highlights the need for accurate memory-centric scheduling mechanisms for guaranteeing prioritized memory accesses to Real-Time safety-related components of the system. We implemented a software technique called cache coloring that demonstrates that isolation at timing and spatial level can be achieved by managing the lines that can be evicted in the cache. In order to show the effectiveness of this technique, the timing properties of a real application are considered as a use case, this application is made of parallel tasks that show different trade-offs between computation and memory loads.Keywords: Real-Time systems · Multi-core · Determinism · Memory interference.3 Safety-critical software guidelines in different domains like ISO-26262 or IEC-61508 [6] are quite similar in many technical aspects.

Contending memory in heterogeneous SoCs: Evolution in NVIDIA Tegra embedded platforms

“…10 shows a clear increase both in the average and maximum recorded latency (6x to 10x), as well as in the width of the curve. As corroborated by previous findings [9], the main cause is the increased probability of a miss in the L2 shared and contended cache for the interrupt service routine's instructions and data, but also from other contention points in the memory hierarchy. Memory access contention is a significant threat also to the worst-case response time.…”

“…For instance, more than one CPU core sharing a common cache level causes uncontrolled eviction of useful cache lines; at system memory level, undisclosed arbitration policies in memory controllers might severely impact latencies when multiple clients are accessing memory in overlapping time windows. A platform-specific characterization of such problems is mandatory before attempting to design adhoc mitigation solutions for memory contention [8], [9].…”

The Predictable Execution Model in Practice

“…We verify the correctness of the compiled PREM tasks, by ensuring that cache misses during the program execution only occur in the memory phase, and evaluate the performance achieved by the transformed code. For these experiments, the runtime is based around the Jailhouse hypervisor [27] featuring cache colored [28,38] inmates (VMs). Cache coloring ensures isolation of cache lines between cores by assigning a fixed number of cache sets to each core.…”