The interplay between structure and function in redox-based resistance switching

Kenyon, Anthony J.; Munde, M; Ng, Wing H.; Buckwell, M; Joksas, Dovydas; Mehonić, Adnan

doi:10.1039/c8fd00118a

Cited by 16 publications

(12 citation statements)

References 20 publications

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“…Figure 2A demonstrates typical set and reset switching curves and two clearly defined resistance states—low resistance state (LRS) and high resistance state (HRS). More details of all switching characteristics, including retention, endurance, variability, as well as further information about the mechanism of the switching process and the microstructure of the SiO x layers, can be found in our previous publications (Mehonic et al, 2015, 2017, 2018; Munde et al, 2017; Kenyon et al, 2019). In this paper, we focus on obtaining multiple intermediate resistance states, which are crucial for implementing programmable weights in neural networks.…”

Section: Resultsmentioning

confidence: 99%

Simulation of Inference Accuracy Using Realistic RRAM Devices

Mehonić

Joksas

et al. 2019

Front. Neurosci.

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Resistive Random Access Memory (RRAM) is a promising technology for power efficient hardware in applications of artificial intelligence (AI) and machine learning (ML) implemented in non-von Neumann architectures. However, there is an unanswered question if the device non-idealities preclude the use of RRAM devices in this potentially disruptive technology. Here we investigate the question for the case of inference. Using experimental results from silicon oxide (SiO x ) RRAM devices, that we use as proxies for physical weights, we demonstrate that acceptable accuracies in classification of handwritten digits (MNIST data set) can be achieved using non-ideal devices. We find that, for this test, the ratio of the high- and low-resistance device states is a crucial determinant of classification accuracy, with ~96.8% accuracy achievable for ratios >3, compared to ~97.3% accuracy achieved with ideal weights. Further, we investigate the effects of a finite number of discrete resistance states, sub-100% device yield, devices stuck at one of the resistance states, current/voltage non-linearities, programming non-linearities and device-to-device variability. Detailed analysis of the effects of the non-idealities will better inform the need for the optimization of particular device properties.

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Section: Resultsmentioning

confidence: 99%

Simulation of Inference Accuracy Using Realistic RRAM Devices

Mehonić

Joksas

et al. 2019

Front. Neurosci.

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“…This is in contrast with the dramatic BD event observed in the as‐exfoliated (untreated) MoS 2 stacks. Therefore, the amount of local defects in the LD plays a very important role defining its BD effect (as it happens in traditional 3D dielectrics like HfO 2 and SiO 2 ). Luckily, the amount of defects can be controlled by using different fabrication methods and postprocessing steps (annealing, plasma etching) stack …”

Section: Layered Dielectricsmentioning

confidence: 99%

A Review on Dielectric Breakdown in Thin Dielectrics: Silicon Dioxide, High‐k, and Layered Dielectrics

Palumbo

Wen

Lombardo

et al. 2019

Adv Funct Materials

163

104

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Thin dielectric films are essential components of most micro-and nanoelectronic devices, and they have played a key role in the huge development that the semiconductor industry has experienced during the last 50 years. Guaranteeing the reliability of thin dielectric films has become more challenging, in light of strong demand from the market for improved performance in electronic devices. The degradation and breakdown of thin dielectrics under normal device operation has an enormous technological importance and thus it is widely investigated in traditional dielectrics (e.g., SiO 2 , HfO 2 , and Al 2 O 3 ), and it should be further investigated in novel dielectric materials that might be used in future devices (e.g., layered dielectrics). Understanding not only the physical phenomena behind dielectric breakdown but also its statistics is crucial to ensure the reliability of modern and future electronic devices, and it can also be cleverly used for other applications, such as the fabrication of new-concept resistive switching devices (e.g., nonvolatile memories and electronic synapses). Here, the fundamentals of the dielectric breakdown phenomenon in traditional and future thin dielectrics are revised. The physical phenomena that trigger the onset, structural damage, breakdown statistics, device reliability, technological implications, and perspectives are described.

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“…The next non‐ideality concerns the cycle‐to‐cycle and device‐to‐device variability that is inherent to nanoscale devices. This could be addressed partially by improved materials engineering, such as the use of ultra‐thin atomic layer deposition‐TiN buffer layers, [ 92 ] or the engineering of oxide–metal interfaces [ 93,94 ] and oxide microstructure [ 95 ] that improves the stability of operating characteristics. These techniques are used to restrict filaments formation to the particular sites and limit significant variations in filaments configuration from cycle to cycle.…”

Section: Some Challenges Of Memristor Technologiesmentioning

confidence: 99%

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

Mehonić¹,

Sebastian

Rajendran

et al. 2020

Advanced Intelligent Systems

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181

121

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Three factors are currently driving the main developments in artificial intelligence (AI): availability of vast amounts of data, continuous growth in computing power, and algorithmic innovations. Graphics processing units (GPUs) have been demonstrated as effective co-processors for the implementation of machine learning (ML) algorithms based on deep learning (DL). Solutions based on DL and GPU implementations have led to massive improvements in many AI tasks, but have also caused an exponential increase in demand for computing power. Recent analyses show that the demand for computing power has increased by a factor of 300 000 since 2012, and the estimate is that this demand will double every 3.4 months-at a much faster rate than improvements made historically through Moore's scaling (a sevenfold improvement over the same period of time). [1] At the same time, Moore's law has been slowing down significantly for the last few years, [2] as there are strong indications that we will not be able to continue scaling down complementary metal-oxide-semiconductor (CMOS) transistors. This calls for the exploration of alternative technology roadmaps for the development of scalable and efficient AI solutions. Transistor scaling is not the only way to improve computing performance. Architectural innovations, such as GPUs, field-programmable arrays (FPGAs), and application-specific integrated circuits (ASICs), have all significantly advanced the ML field. [3] A common aspect of modern computing architectures for ML is a move away from the classical von-Neumann architecture that physically separates memory and computing. This approach yields a performance bottleneck that is often the main reason for both energy and speed inefficiency of ML implementations on conventional hardware platforms due to

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The interplay between structure and function in redox-based resistance switching

Cited by 16 publications

References 20 publications

Simulation of Inference Accuracy Using Realistic RRAM Devices

Simulation of Inference Accuracy Using Realistic RRAM Devices

A Review on Dielectric Breakdown in Thin Dielectrics: Silicon Dioxide, High‐k, and Layered Dielectrics

Memristors—From In‐Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio‐Inspired Computing

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