The influence of TiN ARC thickness on stress-induced void formation in tungsten-plug vias

Walls, James

doi:10.1109/16.644639

Cited by 12 publications

(5 citation statements)

References 12 publications

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“…Therefore, the ratio of for narrow to wide line/via structure is given by (2) where the superscripts narrow and wide correspond to the narrow and wide line/via, respectively. The subscript int refers to the interface current density at the line/via bottom interface, and is the difference in activation energies of the narrow and wide line/via structures which is found to be eV as computed previously.…”

Section: Via Bottom Current Density Dependencymentioning

confidence: 99%

Current crowding effect on copper dual damascene via bottom failure for ULSI applications

Tan

Roy

Vairagar

et al. 2005

IEEE Trans. Device Mater. Relib.

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Reliability of interconnect via is increasing an important issue in submicron technology. Electromigration experiments are performed on line/via structures in two level Cu dual damascene interconnection system and it is found that wide line/via fails earlier than the narrow line/via. Atomic flux divergence based finite element analyses is performed and stress-migration is found to be important in the failure rate behavior observed. Semi-classical width dependence Black's equation together with the finite element analysis revealed that the difference in the time to failure is due to the much larger average current density along the interface between the line and via for the wide line/via structure, and good agreement is obtained between the simulation and experimental results.

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Section: Via Bottom Current Density Dependencymentioning

confidence: 99%

Current crowding effect on copper dual damascene via bottom failure for ULSI applications

Tan

Roy

Vairagar

et al. 2005

IEEE Trans. Device Mater. Relib.

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“…Table 2 summarizes the contribution from the various mechanisms of EM at the three stress conditions. In all three cases, the dominant mechanism found is SM, which is consistent with the reports from other works [47,74].…”

Section: Finite Element Modelingsupporting

confidence: 92%

Realistic modeling of electromigration in today�??s ULSI interconnections

Li¹

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“…Once the current density in an interconnect line exceeds the maximum current-carrying capacity J max of the conductor, the material fails due to the displacement of atoms along the path of electrons, resulting in voids, and such a mechanism is known as electromigration. The J max of Cu is 2.5 MA cm −2 [20] and 1 MA cm −2 for W [21,22]. In order to extend the J max for Cu and W, material engineering approaches such as stress engineering and capping are employed [2].…”

Section: Introductionmentioning

confidence: 99%

Effect of improved contact on reliability of sub-60 nm carbon nanotube vias

et al. 2016

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Advances in semiconductor technology due to the aggressive downward scaling of on-chip feature sizes have led to rapid rises in the resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials are being actively considered as potential replacements to meet such constraints. The carbon nanotube (CNT) is among the leading replacement candidates for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior current-carrying capacity to Cu and W, as well as other potential candidates. Based on the results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering facilitated by the first reported contact resistance extraction scheme for a 40 nm linewidth.

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The influence of TiN ARC thickness on stress-induced void formation in tungsten-plug vias

Cited by 12 publications

References 12 publications

Current crowding effect on copper dual damascene via bottom failure for ULSI applications

Current crowding effect on copper dual damascene via bottom failure for ULSI applications

Realistic modeling of electromigration in today�??s ULSI interconnections

Effect of improved contact on reliability of sub-60 nm carbon nanotube vias

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