The influence of processor architecture on the design and the results of WCET tools

Heckmann, Reinhold; Langenbach, Marc; Thesing, Stephan; Wilhelm, Reinhard

doi:10.1109/jproc.2003.814618

Cited by 189 publications

(130 citation statements)

References 14 publications

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“…If it is not in cache, then a cache miss occurs, and the information is fetched from external memory. Caches are highly beneficial, greatly reducing the WCET of a task in comparison to its WCET if executed directly from external memory, provided they are well-designed [Heckmann et al 2003;Wilhelm et al 2009]. …”

Section: Real-time Systems Sharing the Cachementioning

confidence: 99%

Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Whitham

Audsley

Davis

2014

ACM Trans. Embed. Comput. Syst.

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We describe and evaluate explicit reservation of cache memory to reduce the cache-related preemption delay (CRPD) observed when tasks share a cache in a preemptive multitasking hard real-time system. We demonstrate the approach using measurements obtained from a hardware prototype, and present schedulability analyses for systems that share a cache by explicit reservation. These analyses form the basis for a series of experiments to further evaluate the approach. We find that explicit reservation is most useful for larger task sets with high utilization. Some task sets cannot be scheduled with a conventional cache, but are schedulable with explicit reservation.

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Section: Real-time Systems Sharing the Cachementioning

confidence: 99%

Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Whitham

Audsley

Davis

2014

ACM Trans. Embed. Comput. Syst.

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“…The most problematic processor features for WCET analysis are the replacement strategies for set-associative caches [14]. A pseudo-round-robin replacement strategy of the 4-way set-associative cache in the ColdFire MCF 5307 effectively renders the associativity useless for WCET analysis.…”

Section: Related Workmentioning

confidence: 99%

“…Such an integrated analysis is complex and also demanding with respect to the computational effort. Consequently, Heckmann et al [14] suggest the following restrictions for time-predictable processors: (1) separate data and instruction caches; (2) locally deterministic update strategies for caches; (3) static branch prediction; and (4) limited out-of-order execution. Further suggestions for time-predictable architectures and memory hierarchies are given in [57].…”

Section: Related Workmentioning

confidence: 99%

Data cache organization for accurate timing analysis

2012

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Caches are essential to bridge the gap between the high latency main memory and the fast processor pipeline. Standard processor architectures implement two first-level caches to avoid a structural hazard in the pipeline: an instruction cache and a data cache. For tight worst-case execution times it is important to classify memory accesses as either cache hit or cache miss. The addresses of instruction fetches are known statically and static cache hit/miss classification is possible for the instruction cache. The access to data that is cached in the data cache is harder to predict statically. Several different data areas, such as stack, global data, and heap allocated data, share the same cache. Some addresses are known statically, other addresses are only known at runtime. With a standard cache organization all those different data areas must be considered by worst-case execution time analysis. In this paper we propose to split the data cache for the different data areas. Data cache analysis can be performed individually for the different areas. Access to an unknown address in the heap does not destroy the abstract cache state for other data areas. Furthermore, we propose to use a small, highly associative cache for the heap area. We designed and implemented a static analysis for this cache, and integrated it into a worst-case execution time analysis tool.

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“…An upper bound on the execution time of an individual task is commonly referred to as the worst-case execution time (WCET) of the task. WCET analysis is a difficult problem, depending on the processor architecture and the task implementation [15]. For example, memory caches and processor pipelines often improve average performance significantly but are inherently context-sensitive concepts and therefore complicate WCET analyses, in particular, if tight WCET bounds are needed.…”

Section: The Computing Abstractions Of Control Engineeringmentioning

confidence: 99%