Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Whitham, Jack; Audsley, Neil; Davis, Robert I.

doi:10.1145/2523070

Cited by 11 publications

(7 citation statements)

References 30 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…Furthermore scratchpad management may be either static or dynamic. With a static scratchpad management, the scratchpad contents remain constant throughout operation, whereas with dynamic scratchpad management, scratchpad blocks can be reloaded as needed, for example on pre-emptions, which makes better use of the available scratchpad memory (Whitham et al 2012(Whitham et al , 2014.…”

Section: Scratchpadsmentioning

confidence: 99%

“…These are used to represent the memory blocks of a task that are stored in the scratchpad. A tighter integration, which requires dedicated hardware support is described by Whitham et al (2012Whitham et al ( , 2014; however, analysis for it is beyond the scope of this paper. As in the static case, a scratchpad memory is defined using a function SPM : M → {true, f alse}, which returns true for memory blocks that are stored in the scratchpad.…”

Section: Dynamic Scratchpadsmentioning

confidence: 99%

See 1 more Smart Citation

An extensible framework for multicore response time analysis

et al. 2017

Self Cite

View full text Add to dashboard Cite

In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

show abstract

Section: Scratchpadsmentioning

confidence: 99%

Section: Dynamic Scratchpadsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

Self Cite

View full text Add to dashboard Cite

show abstract

“…A system for explicit reservation of cache memory [95], where the state of the cache memory is saved before a preemption and restored before the preempted task is resumed. The cache state is restored in a single operation before the task is resumed instead of multiple cache misses after the task has been resumed.…”

Section: Cachesmentioning

confidence: 99%

Timing Predictability in Future Multi-Core Avionics Systems

Löfwenmark¹

2017

View full text Add to dashboard Cite

With more functionality added to safety-critical avionics systems, new platforms are required to offer the computational capacity needed. Multi-core platforms offer a potential that is now being explored, but they pose significant challenges with respect to predictability due to shared resources (such as memory) being accessed from several cores in parallel. Multi-core processors also suffer from higher sensitivity to permanent and transient faults due to shrinking transistor sizes.This thesis addresses several of these challenges. First, we review major contributions that assess the impact of fault tolerance on worst-case execution time of processes running on a multi-core platform. In particular, works that evaluate the timing effects using fault injection methods. We conclude that there are few works that address the intricate timing effects that appear when inter-core interferences due to simultaneous accesses of shared resources are combined with the fault tolerance techniques. We assess the applicability of the methods to COTS multi-core processors used in avionics. We identify dark spots on the research map of the joint problem of hardware reliability and timing predictability for multi-core avionics systems.Next, we argue that the memory requests issued by the real-time operating systems (RTOS) must be considered in resource-monitoring systems to ensure proper execution on all cores.We also adapt and extend an existing method for worst-case response time analysis to fulfill the specific requirements of avionics systems. We relax the requirement of private memory banks to also allow cores to share memory banks.

show abstract

“…Explicit reservation of cache memory to reduce worst case cache-related preemption delay (CRPD) was proposed in [84], where the state of cache is saved to the stack during preemption and restored when the task continues execution. This technique induces a constant CRPD regardless of the task being preempted, but increases CRPD when no or few cache blocks are shared between pre-empting and pre-empted tasks.…”

Section: Related Workmentioning

confidence: 99%

Hardware architecture support for mixed criticality and real-time systems

Govindaiah¹,

Kumar²

View full text Add to dashboard Cite

Explicit reservation of cache memory in a predictable, preemptive multitasking real-time system

Cited by 11 publications

References 30 publications

An extensible framework for multicore response time analysis

An extensible framework for multicore response time analysis

Timing Predictability in Future Multi-Core Avionics Systems

Hardware architecture support for mixed criticality and real-time systems

Contact Info

Product

Resources

About