The importance of using dual channel heterostructure in strained P-MOSFETs

Taberkit, Amine Mohammed; Guen-Bouazza, A.; Horch, Mohamed

doi:10.1109/ccee.2018.8634492

Cited by 2 publications

(2 citation statements)

References 6 publications

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“…On the other hand, since strained silicon devices are scalable while also enhancing carrier mobility due to its strain quantization effect, it does not hinder the scaling of the nano devices into Quantum Well Barrier systems achievable at sub-20 nm regime. The strained devices are known to improve the mobility of the charge carriers, achieving aggravated drain currents is inevitable [13][14][15][16][17][18]. Strain is incorporated by innumerable researchers either as local or global strain by growing strained silicon (s-Si) layer on silicon-germanium (Si 1-x Ge x ) or by growing s-Si layer on strained Si 1-x Ge x .…”

Section: Introductionmentioning

confidence: 99%

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Nanda,

Dhar

2024

Phys. Scr.

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3D FinFETs are meticulously scaled down to sub-14 nm leading to reemerging undesirable characteristics namely increased Drain Induced Barrier Leakage (DIBL), higher subthreshold swing and excessive leakage currents. This inhibits the scaling of FinFETs and research suggests probable utilization of strained silicon technology in FinFETs to improve the on currents and transconductance of the nano devices. The emergence of quantum effects including velocity overshoot and carrier confinement severely affects the electrical characteristics at sub-10 nm channel length devices. Therefore, amalgamation of strained silicon prove to be a boon in FinFETs while being at par with the proposed 3 nm technology node of IRDS 2018, and designing to develop reliable devices at 08 nm gate length is the requisite. Thus, exploring the design and performance investigation of novel 08 nm Quantum Well FinFETs (QW-FinFETs) incorporating a tri-layered strained silicon Heterostructure-On-Insulator (HOI)are proposed with distinct channel dimensions which are analyzed and compared with existing devices. The optimum QW-FinFET device developed for 3 nm technology node of IRDS 2018 achieved a ~25% enhancement in drain currents with Device D2 portraying almost ~103% escalations in electron mobility on account of ballistic transport of charge carriers without scattering and enriching the performance for the future generation of device resulting in faster switching operation in sub-nano regime.

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Section: Introductionmentioning

confidence: 99%

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Nanda,

Dhar

2024

Phys. Scr.

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“…SiGe also has the same crystallographic structure as Si, but its lattice constant is larger by 4.2% for pure Ge [6]. By using strained-SiGe, 2-3 times classic Si MOSFET performance improvements are obtained [6][7][8]. Starting with the 90 nm CMOS technology node, embedded SiGe source/drain (S/D) were used to increase the p-MOSFET drive current by introducing compressive strain into the channel [9].…”

Section: Introductionmentioning

confidence: 99%

Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness

Salleh

Rahim

Razali

et al. 2023

KEM

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Compressively strained SiGe is an interesting channel material for sub 45 nm p-MOSFETs because of its superior hole mobility (up to 10x over bulk Si channels) and compatibility with current Si manufacturing technologies. In this work, the impact of heterostructure composition and SiGe channel thickness on the electrical characteristics of p-MOSFET are studied. Using strained Si0.8Ge0.2 p-MOSFET, the thickness was altered to a few thicknesses of 3 nm, 5 nm, 7 nm, and 9 nm respectively. The optimal thickness was then used for Ge compositions (x = 0.2). The project was realized utilizing computer-aided Silvaco TCAD tools, with ATHENA tools creating the p-MOSFET structure and ATLAS tools doing the device simulation. The strained-Si1-xGex p-MOSFET and the Si p-MOSFET were compared in terms of their performances. The ID-VG and ID-VD characteristics, as well as the threshold voltage, VTH extraction, were the focus of the device simulation. The 7 nm thickness strained-Si0.8Ge0.2 p-MOSFET exhibited lower VTH than other SiGe thicknesses and the Si p-MOSFET which is VTH = 0.074 V. The lower threshold voltage of the strained-Si0.8Ge0.2 with 7 nm thickness indicating that the strained-Si1-xGex contributed to the decreased power consumption. In addition, the extracted IDsat for the strained-Si0.8Ge0.2 p-MOSFET with 7nm thickness provided higher IDsat compared to conventional Si p-MOSFET and other SiGe thicknesses devices. As compared to Si p-MOSFETs, the output characteristics of the strained-Si1-xGex demonstrated a drain current improvement by a factor of 1.01.

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The importance of using dual channel heterostructure in strained P-MOSFETs

Cited by 2 publications

References 6 publications

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Evolution and performance analysis of quantum well FinFET for 3 nm technology node with type-II strained tri-layered hetero-channel system

Study of Strained-SiGe Channel P-MOSFET Using Silvaco TCAD: Impact of Channel Thickness

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