The Impact of Self-Heating on HCI Reliability in High-Performance Digital Circuits

Jiang, Hai; Shin, Sanghoon; Liu, Xiaoyan; Xing, Zongyi; Alam, Muhammad Ashraful

doi:10.1109/led.2017.2674658

Cited by 40 publications

(26 citation statements)

References 9 publications

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“…52,53 Besides, the thermal resistance (R th ) of the multi-gate topology and the reduced gate pitch in Fin-FET devices exacerbate self-heating which will accelerate aging. 54 Figure 16 shows our simulation results with the industrial aging models; the results show a very significant performance degradation under accelerated stress condition, and if we scale this to the normal operating condition (nominal V dd and normal on-chip temperature), the degradation is still much larger than that in the planar devices. For interconnect reliability, EM no longer can be signed off using aggressive margins, a comprehensive thermalaware EM signoff methodology needs to be adopted for FinFET designs.…”

Section: Variability and Reliabilitymentioning

confidence: 98%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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It has been almost a decade since FinFET devices were introduced to full production; they allowed scaling below 20 nm, thus helping to extend Moore's law by a precious decade with another decade likely in the future when scaling to 5 nm and below. Due to superior electrical parameters and unique structure, these 3-D transistors offer significant performance improvements and power reduction compared to planar CMOS devices. As we are entering into the sub-10 nm era, FinFETs have become dominant in most of the high-end products; as the transition from planar to FinFET technologies is still ongoing, it is important for digital circuit designers to understand the challenges and opportunities brought in by the new technology characteristics. In this paper, we study these aspects from the device to the circuit level, and we make detailed comparisons across multiple technology nodes ranging from conventional bulk to advanced planar technology nodes such as Fully Depleted Silicon-on-Insulator (FDSOI), to FinFETs. In the simulations we used both state-of-art industry-standard models for current nodes, and also predictive models for future nodes. Our study shows that besides the performance and power benefits, FinFET devices show significant reduction of short-channel effects and extremely low leakage, and many of the electrical characteristics are close to ideal as in old long-channel technology nodes; FinFETs seem to have put scaling back on track! However, the combination of the new device structures, double/multi-patterning, many more complex rules, and unique thermal/reliability behaviors are creating new technical challenges. Moving forward, FinFETs still offer a bright future and are an indispensable technology for a wide range of applications from high-end performance-critical computing to energy-constraint mobile applications and smart Internet-of-Things (IoT) devices.

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Section: Variability and Reliabilitymentioning

confidence: 98%

Back to the Future: Digital Circuit Design in the FinFET Era

Guo¹,

Verma²,

Gonzalez-Guerrero³

et al. 2017

Journal of Low Power Electronics

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“…Let us assume ℎ, − = ( ) −1 , where is the device width, is the substrate thermal conductivity, and is the shape factor [41]. In practice, one can easily obtain the shape factor for a technology from thermal modeling and/or experimental measurements [16]- [17]. Note that effective ℎ, − (for the packaged chip) can change with duty cycle and frequency, as discussed in Section IV.…”

Section: A Analytical Derivationsmentioning

confidence: 99%

“…At = 300 K, by setting , = 450 K, can be determined using the following relation: is the pulse duration ( = , is the period, is the duty cycle). Considering multiple stages of equivalent RC-time constants due to package, submounts, heat sink, PCB, etc., one can write [17], [18]:…”

Section: Self-heating Aware Intrinsic Soa For Wbg Semiconductorsmentioning

confidence: 99%

Self-Heating and Reliability-Aware “Intrinsic” Safe Operating Area of Wide Bandgap Semiconductors—An Analytical Approach

Mahajan

Zagni

2021

IEEE Trans. Device Mater. Relib.

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The emergence of several technology options and the ever-broadening range of applications (e.g., automotive, smart grids, solar/wind farms) for power electronic devices suggest both a need and an opportunity to develop unifying principles to guide the development of wide bandgap (WBG) semiconductors. Unfortunately, power electronic devices are typically evaluated with a variety of elementary figure of merits (FOMs), which offer inconsistent/contradictory projections regarding the relative merits of emerging technologies. Indeed, one relies on the empirical (extrinsic) safe-operating area (SOA) of a packaged device to ultimately assess the performance potential of a technology option. Unfortunately, extrinsic SOA can only be calculated a posteriori, i.e., after precise measurement of the fabricated device parameters, making it suitable only for relatively mature technologies. Based on the insights of material-devicecircuit-system performance analysis of a variety of idealized WBG power electronic devices (e.g., GaN HEMT, β-Ga2O3 MOSFET), in this paper, we analytically derive a comprehensive, substrate-, self-heating-, and reliability-aware "intrinsic/limiting" safe operating area (SOA) that establishes a priori, i.e., before device fabrication, the optimum and self-consistent trade-off among breakdown voltage, power consumption, operating frequency, heat dissipation, and reliability. We establish the relevance of the intrinsic-SOA by comparing its prediction with a broad range of experimental data available in the literature. In between the traditional FOMs and extrinsic SOA, the intrinsic SOA allows fundamental/intuitive re-evaluation of intrinsic technology potential for power electronic devices and identifies specific performance bottlenecks and how to circumvent them.

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“…SHE is well studied at the transistor level since it is well known for Silicon-On-Insulator (SOI) devices [8] and power MOSFETs [9]. Recently, transistor-level studies in FinFETs provide a good understanding of SHE in transistors [10] [11] [12]. However, these studies are limited to simple circuits and the impact of SHE beyond ring oscillators and SRAM cells is not yet studied.…”

Section: Related Workmentioning

confidence: 99%

“…b) SHE: SHE is well studied at the transistor-level since it is well known for Silicon On Insulator (SOI) device [26] and power MOSFETs [27]. Recently, transistor-level studies in FinFETs [12] [13] [28] provide a good understanding of SHE per transistor. However, the impact of SHE beyond ring oscillators and SRAM cells is not yet studied as SHE is absent in EDA flow limiting the scope of their studies, due to technical limitations (e.g., simulation runtimes).…”

Section: Related Workmentioning

confidence: 99%

Minimizing Excess Timing Guard Banding Under Transistor Self-Heating Through Biasing at Zero-Temperature Coefficient

et al. 2021

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Self-Heating Effects (SHE) is known as one of the key reliability challenges in FinFET and beyond. Large timing guardbands are necessary, which we try to reduce. In this work, we propose operating (biasing) processors at Zero-Temperature Coefficient (ZTC) to contain (mitigate) SHE-induced delay. Operating at ZTC allows near-zero timing guard band to protect circuits against SHE. However, a trade-off is found between thermal timing guardband and performance loss from lowering the voltage.

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The Impact of Self-Heating on HCI Reliability in High-Performance Digital Circuits

Cited by 40 publications

References 9 publications

Back to the Future: Digital Circuit Design in the FinFET Era

Back to the Future: Digital Circuit Design in the FinFET Era

Self-Heating and Reliability-Aware “Intrinsic” Safe Operating Area of Wide Bandgap Semiconductors—An Analytical Approach

Minimizing Excess Timing Guard Banding Under Transistor Self-Heating Through Biasing at Zero-Temperature Coefficient

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