The impact of production defects on the soft-error tolerance of hardened latches

Holst, Stefan; Ma, Ruijun; Wen, Xiaoqing

doi:10.1109/ets.2018.8400694

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Cited by 6 publications

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An ultra low‐power double‐node‐upsets hardened latch design

Chen,

Xie,

Liang

et al. 2024

Circuit Theory & Apps

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In this paper, a novel low‐cost, double‐node upset (DNU) tolerant latch aiming at nourishing the lack of these devices in the state of the art was presented, especially featuring high reliability while maintaining a low‐cost profile. The proposed latch is based on a low‐cost single event double‐node upset tolerant latch and also provides self‐recoverability against double‐node‐upsets. The latch uses clock‐controlled DICE (Dual‐interlocked storage cell) cell and CE(C‐Elements) cell to tolerate double‐node‐upsets fully. The Simulation waveforms and analysis results show that the proposed latch can maintain the correct output in any case of DNU. In addition, under the premise of high radiation tolerance, the minimum improvement of the area‐power‐delay product (APDP) of the proposed low‐power double‐node‐upsets hardened latch (LPDHL) is 16.60%, compared with the latest DNU tolerant latch on the literature.

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