The impact of PMOST bias-temperature degradation on logic circuit reliability performance

Accurate negative bias temperature instability lifetime prediction based on hole injection

“…For the prediction of long time reliability, the electrical stress acceleration is often employed. NBT stress induces the fixed charge in the gate insulator films and surface state at Si/gate insulator interface, as a result, causes the threshold voltage (V th ) shift and degradation of drain current [1][2][3][4][5][6][7][8][9]. For an accurate lifetime prediction, an accurate understanding of the degradation mechanism and an appropriate acceleration method are essentially required.…”

IBM System z9 eFUSE applications and methodology

“…After the initial designs finished long-term reliability testing, a problem with the sense circuitry was discovered. The p-FET P1 [Figure 2(b)] in the half latch used as part of the sense circuitry would weaken over time (because of a voltage-threshold deterioration mechanism known as negative bias temperature instability, or NBTI [4]) if the half latch was storing a 1 value. This happened whenever a programmed fuse was read, and the resulting state would persist until the chip was powered off.…”

Thin-Gate-Oxide Breakdown and CPU Failure-Rate Estimation

“…One way to resolve this is to adjust the V CCMIN after significant circuit operation or to add a build-in guardband to ensure adequate V CC for device drive. For the product evaluation here, adequate built-in margin is included in the product sort and class tests to ensure the circuit is robust for the low level of V CCMIN disturb due to the PMOS NBTI instability or NMOS SBD [6], [7], [32].…”

“…However, similar problem has not been detected in this paper for this technology. This can be attributed to the gate-oxide process improvement [7], cache cell design optimization [34], and reliability test guard band [32].…”