The impact of Moore's Law and loss of Dennard scaling: Are DSP SoCs an energy efficient alternative to x86 SoCs?

Johnsson, Lennart; Netzer, Gilbert

doi:10.1088/1742-6596/762/1/012022

Cited by 13 publications

(8 citation statements)

References 22 publications

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“…Dennard’s scaling theory 1 , 2 has acted as a guideline for the semiconductor industry to miniaturize the metal oxide semiconductor (MOS) technology in order to comply with the Moore’s law 3 . According to this theory, the power density remains constant over technology nodes if both the dimension and supply voltage ( V D ) are scaled by the same factor (known as constant-field scaling).…”

Section: Introductionmentioning

confidence: 99%

Scalability assessment of Group-IV mono-chalcogenide based tunnel FET

Brahma

Kabiraj

Saha

et al. 2018

Sci Rep

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Selection of appropriate channel material is the key to design high performance tunnel field effect transistor (TFET), which promises to outperform the conventional metal oxide semiconductor field effect transistor (MOSFET) in ultra-low energy switching applications. Recently discovered atomically thin GeSe, a group IV mono-chalcogenide, can be a potential candidate owing to its direct electronic band gap and low carrier effective mass. In this work we employ ballistic quantum transport model to assess the intrinsic performance limit of monolayer GeSe-TFET. We first study the electronic band structure by regular and hybrid density functional theory and develop two band k · p hamiltonian for the material. We find that the complex band wraps itself within the conduction band and valence band edges and thus signifies efficient band to band tunneling mechanism. We then use the k · p hamiltonian to calculate self-consistent solution of the transport equations within the non-equilibrium Green’s function formalism and the Poisson’s equation based electrostatic potential. Keeping the OFF-current fixed at 10 pA/μm we investigate different static and dynamic performance metrics (ON current, energy and delay) under three different constant-field scaling rules: 40, 30 and 20 nm/V. Our study shows that monolayer GeSe-TFET is scalable till 8 nm while preserving ON/OFF current ratio higher than 104.

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Section: Introductionmentioning

confidence: 99%

Scalability assessment of Group-IV mono-chalcogenide based tunnel FET

Brahma

Kabiraj

Saha

et al. 2018

Sci Rep

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“…9 Basically until the 65 nm node, the shrinkage of feature-size has continued in line with Dennard scaling, by a factor (S) of 1/ √ 2, to accommodate doubling of transistors per unit chip area (scaling as S 2 = 1/2) every two years in relation to Moore's law. 10 Increased leakage currents in the subsequent feature reductions have eventually shifted this technology trend, with the emergence of advanced multicore systems. 11 While the scaling factor of 1/ √ 2 has been largely maintained in the post-Dennard period, the newer logic devices have evolved in a more complex manner compared to their earlier counterparts.…”

Section: Device Scaling and Cmp Considerationsmentioning

confidence: 99%

Perspective—Electrochemical Assessment of Slurry Formulations for Chemical Mechanical Planarization of Metals: Trends, Benefits and Challenges

Roy¹

2018

ECS J. Solid State Sci. Technol.

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With continued shrinkage of circuit dimensions, the technique of chemical mechanical planarization (CMP) has become progressively more intricate through the last decade. Since the chemical mechanism of metal CMP is governed by electrochemical effects, the complex task of CMP-slurry engineering can be economically assisted in the electroanalytical approach by using laboratory scale model systems. This article discusses how CMP has been impacted by device scaling, and examines the status of fundamental studies of metal CMP. The techniques suitable for studying model CMP systems are discussed, along with an assessment of the utilities and the practical limits of such experiments. Chemical mechanical planarization (CMP) is an essential processing step of integrated circuit (IC) fabrication. 1,2 CMP of the metal components of logic devices constitute a major aspect of this technique and, like other areas of IC manufacturing, metal CMP has become quite complex while addressing the emerging demands of technology through the last decade. 3 The new challenges of metal CMP originate from both the scaling and the novel material aspects of these systems. 3,4 At the same time, published reports indicate that, many of these issues, especially those related to the slurry consumables, 5 can be addressed to a large extent through electroanalytical examinations of slurry functions using scaled down models of actual CMP systems. 6 Recent studies performed in industrial facilities have also identified a critical need to further advance the fundamental understanding of metal CMP. 7,8 The present article provides a perspective on these fundamental research aspects of metal CMP that are in the core of most laboratory scale studies of these systems. Device Scaling and CMP ConsiderationsThe International Technology Roadmap for Semiconductors (ITRS) specified the earlier technology nodes in terms of the DRAM half-pitch (hp), or the microprocessor's level-1 metal hp of a device. 9 Basically until the 65 nm node, the shrinkage of feature-size has continued in line with Dennard scaling, by a factor (S) of 1/ √ 2, to accommodate doubling of transistors per unit chip area (scaling as S 2 = 1/2) every two years in relation to Moore's law. 10 Increased leakage currents in the subsequent feature reductions have eventually shifted this technology trend, with the emergence of advanced multicore systems. 11 While the scaling factor of 1/ √ 2 has been largely maintained in the post-Dennard period, the newer logic devices have evolved in a more complex manner compared to their earlier counterparts. The middle-of-line (MOL) metallization scheme has emerged from the need to reduce the parasitic effects of active wiring that extends over 4 km cm −2 for >13 metal layers. 9 Novel diffusion barriers and ultra-low-k (ULK) dielectrics, Fin field effect transistors (Fin-FETs), high-k gate dielectrics, and exploratory designs/materials for local interconnects have been steadily incorporated in new device architectures in keeping with the advents of scaling sch...

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“…The current computational paradigm is based on the conventional von Neumann architecture, dependent on progress in CMOS transistor performance improvement and scaling, in alignment with Moore's law and Dennard's scaling observations. 1 The von Neumann architecture is designed with separate regions allocated for processing and memory interconnected by data buses. While technological demands have been fulfilled by such an architecture, the growing performance discrepancy between processing and memory units sees an impending limit imposed by performance and scalability.…”

Section: ■ Introductionmentioning

confidence: 99%

Proton-Assisted Redox-Based Three-Terminal Memristor for Synaptic Device Applications

Liu

Dananjaya

Chee

et al. 2023

ACS Appl. Mater. Interfaces

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Emerging technologies, i.e., spintronics, 2D materials, and memristive devices, have been widely investigated as the building block of neuromorphic computing systems. Three-terminal memristor (3TM) is specifically designed to mitigate the challenges encountered by its two-terminal counterpart as it can concurrently execute signal transmission and memory operations. In this work, we present a complementary metal-oxide-semiconductor-compatible 3TM with highly linear weight update characteristics and a dynamic range of ∼15. The switching mechanism is governed by the migration of oxygen ions and protons in and out of the channel under an external gate electric field. The involvement of the protonic defects in the electrochemical reactions is proposed based on the bipolar pulse trains required to initiate the oxidation process and the device electrical characteristics under different humidity levels. For the synaptic operation, an excellent endurance performance with over 256k synaptic weight updates was demonstrated while maintaining a stable dynamic range. Additionally, the synaptic performance of the 3TM is simulated and implemented into a four-layer neural network (NN) model, achieving an accuracy of ∼92% in MNIST handwritten digit recognition. With such desirable conductance modulation characteristics, our proposed 3T-memristor is a promising synaptic device candidate to realize the hardware implementation of the artificial NN.

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The impact of Moore's Law and loss of Dennard scaling: Are DSP SoCs an energy efficient alternative to x86 SoCs?

Cited by 13 publications

References 22 publications

Scalability assessment of Group-IV mono-chalcogenide based tunnel FET

Scalability assessment of Group-IV mono-chalcogenide based tunnel FET

Perspective—Electrochemical Assessment of Slurry Formulations for Chemical Mechanical Planarization of Metals: Trends, Benefits and Challenges

Proton-Assisted Redox-Based Three-Terminal Memristor for Synaptic Device Applications

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