The impact of exploiting instruction-level parallelism on shared-memory multiprocessors

Abstract

AbstractÐCurrent microprocessors incorporate techniques to aggressively exploit instruction-level parallelism (ILP). This paper evaluates the impact of such processors on the performance of shared-memory multiprocessors, both without and with the latencyhiding optimization of software prefetching. Our results show that, while ILP techniques substantially reduce CPU time in multiprocessors, they are less effective in removing memory stall time. Consequently, despite the inherent latency tolerance features of ILP processors, we find memory system performance to be a larger bottleneck and parallel efficiencies to be generally poorer in ILPbased multiprocessors than in previous generation multiprocessors. The main reasons for these deficiencies are insufficient opportunities in the applications to overlap multiple load misses and increased contention for resources in the system. We also find that software prefetching does not change the memory bound nature of most of our applications on our ILP multiprocessor, mainly due to a large number of late prefetches and resource contention. Our results suggest the need for additional latency hiding or reducing techniques for ILP systems, such as software clustering of load misses and producer-initiated communication.

Role of Multiblocks in Control Flow Prediction using Parallel Register Sharing Architecture

“…This facilitates INSTRUCTION LEVEL PARALLELISM with loop as combined optimization. The impact of ILP processors on the performance of shared memory multiprocessors [17] with and without latency hiding optimizing software prefetching has been represented by Pai, Ranganathan, Shafi andAdve (1999). One of the critical goals in the code optimization for multiprocessor system on single chip architecture [4] is to minimize the number of off chip memory access.…”

A Modern Parallel Register Sharing Architecture for Code Compilation

“…[20 ] represents the impact of ILP processors on the performance of shared-memory multiprocessors, both without and with the latency hiding optimization of software pre-fetching. One of the critical goals in code optimization for Multiprocessor-System-on-a-Chip (MPSoC) architectures is to minimize the number of off-chip memory accesses.…”

Code transformations to improve memory parallelism

“…The graph shows multiprocessor and uniprocessor experiments (MP/UP) before and after clustering (Base/Clust), normalized to the given application and system size without clustering. For analysis, execution time is categorized into data memory stall, CPU, synchronization stall, and instruction memory stall times, following the conventions of previous work (e.g., [14]). Since writes can retire before completing and read hits are fast, nearly all data memory stalls stem from reads that miss in the L2 cache.…”

“…Our previous work characterized the effectiveness of ILP processors in a shared-memory multiprocessor [14]. Although ILP techniques successfully and consistently reduced the CPU component of execution time, their impact on the memory (read) stall component was lower and more application-dependent, making read stall time a larger bottleneck in ILP-based multiprocessors than in previousgeneration systems.…”

“…However, prefetching can be less effective in ILP systems because of increased late prefetches and resource contention [14]. We only consider read miss clustering in this work; our ongoing investigations indicate ways in which clustering transformations can also improve the effectiveness of prefetching [13].…”