The impact of delay on the design of branch predictors

Jiménez, Daniel; Keckler, Stephen W.; Lin, Calvin

doi:10.1109/micro.2000.898059

Cited by 53 publications

(84 citation statements)

References 17 publications

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“…However, a previous study on branch prediction delay shows that a relatively accurate single-cycle latency predictor outperforms a 100% accurate predictor with two cycles of latency [2].…”

Section: Accuracy Vs Delaymentioning

confidence: 90%

A Power-Aware Alternative for the Perceptron Branch Predictor

Aasaraai

Baniasadi

Advances in Computer Systems Architecture

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Abstract. The perceptron predictor is a highly accurate branch predictor. Unfortunately this high accuracy comes with high complexity. The high complexity is the result of the large number of computations required to speculate each branch outcome.In this work we aim at reducing the computational complexity for the perceptron predictor. We show that by eliminating unnecessary data from computations, we can reduce both predictor's power dissipation and delay. We show that by applying our technique, predictor's dynamic and static power dissipation can be reduced by up to 52% and 44% respectively. Meantime we improve performance by up to 16% as we make faster prediction possible.

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“…However, a previous study on branch prediction delay shows that a relatively accurate single-cycle latency predictor outperforms a 100% accurate predictor with two cycles of latency [2].…”

Section: Accuracy Vs Delaymentioning

confidence: 90%

A Power-Aware Alternative for the Perceptron Branch Predictor

Aasaraai

Baniasadi

Advances in Computer Systems Architecture

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“…In addition, the fetch address generation should be done in a single cycle because this address is needed for fetching instructions in the next cycle. However, the increase in processor clock frequency, as well as the slower wires in modern technologies, cause branch prediction tables to require multi-cycle accesses [1,10].…”

Section: Related Workmentioning

confidence: 99%

“…A different approach is the overriding mechanism described by Jimenez et al [10]. This mechanism provides two predictions, a first prediction coming from a fast branch predictor, and a second prediction coming from a slower, but more accurate predictor.…”

Section: Prediction Overridingmentioning

confidence: 99%

“…The continuous increase in processor clock frequency, as well as the larger wire latencies caused by modern technologies, prevent branch prediction tables from being accessed in a single cycle [1,10]. In spite of this, the fetch address generation should be done in a single cycle to allow fetching instructions in the next cycle.…”

Section: Introductionmentioning

confidence: 99%

“…A slower but more accurate predictor provides a new prediction some cycles later, overriding the first prediction if they differ [10,26]. Prediction overriding involves discarding the speculative work done based on the overridden prediction.…”

Section: Introductionmentioning

confidence: 99%

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Latency tolerant branch predictors

Santana

Ramírez

Valero

Innovative Architecture for Future Generation High-Performance Processors and Systems, 2003

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A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

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Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing the latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers, and researchers. KEYWORDSdynamic branch predictor, hybrid BP, neural BP, perceptron predictorside BP, pipelining, predictor accuracy, review, side BP, speculative execution, two-level BP INTRODUCTIONControl-changing instructions such as branches add uncertainty in the execution of dependent instructions and thus lead to large performance loss in pipelined processors. To offset their overhead, accurate prediction of branch outcomes is vital. Since branch misprediction incurs high latency (eg, 14 to 25 cycles 1 ) and wastes energy due to execution of instructions on wrong-path, an improvement in BP* accuracy can boost performance and energy efficiency significantly. For example, experiments on real processors showed that reducing the branch mispredictions by half improved the processor performance by 13%. 2Effective design and management of BPs, however, presents several challenges. Design of BP involves a strict tradeoff between area, energy, accuracy, and latency. An increase in BP complexity for improving accuracy may make it infeasible for implementation or offset its performance benefit. For example, a 512 KB perceptron predictor may provide lower instruction-per-cycle than its 32 KB version, 3 and a 2-cycle fully accurate BP may provide lower instruction-per-cycle than a 1-cycle partially inaccurate BP. 4 Further, due to its high access frequency, BP becomes a thermal hot-spot, 5 and hence, reducing its dynamic and leakage energy is important. Clearly, intelligent techniques are required for resolving these issues.Further, recently, researchers have demonstrated two security vulnerabilities viz., "Meltdown" and "Spectre," which exploit speculative execution feature of modern CPUs. 6-8 For example, Spectre vulnerability works on the observation that the speculative execution due to a branch misprediction may leave side effects, which can reveal sensitive data to attackers, eg, if the memory accesses performed during speculative execution depends on sensitive data, the resulting state of the cache forms a side-channel through which the sensitive data can be leaked. These vulnerabilities affect nearly every modern CPU. While avoiding speculative execution (eg, disabling branch prediction) can mitigate these vulnerabilities, it leads to significant performance loss. In light of these vulnerabilities and associated tradeoffs, a deeper study of branch predictors is definitely required. Contributions:In this ...

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The impact of delay on the design of branch predictors

Abstract: Abstract

Cited by 53 publications

References 17 publications

A Power-Aware Alternative for the Perceptron Branch Predictor

A Power-Aware Alternative for the Perceptron Branch Predictor

Latency tolerant branch predictors

A survey of techniques for dynamic branch prediction

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