Latency tolerant branch predictors

Santana, Oliverio J.; Ramírez, Alex; Valero, Mateo

doi:10.1109/iwia.2003.1262780

Cited by 8 publications

(14 citation statements)

References 25 publications

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“…A stream prediction contains enough instructions to feed the execution engine during multiple cycles [6]. Therefore, the longer a stream is, the more cycles the execution engine will be busy without requiring a new prediction.…”

Section: Introductionmentioning

confidence: 99%

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Enlarging Instruction Streams

Desmet

Verbaeten

Joosen

et al. 2007

IEEE Trans. Comput.

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Abstract-The stream fetch engine is a high-performance fetch architecture based on the concept of an instruction stream. We call a sequence of instructions from the target of a taken branch to the next taken branch, potentially containing multiple basic blocks, a stream. The long length of instruction streams makes it possible for the stream fetch engine to provide a high fetch bandwidth and to hide the branch predictor access latency, leading to performance results close to a trace cache at a lower implementation cost and complexity. Therefore, enlarging instruction streams is an excellent way to improve the stream fetch engine. In this paper, we present several hardware and software mechanisms focused on enlarging those streams that finalize at particular branch types. However, our results point out that focusing on particular branch types is not a good strategy due to Amdahl's law. Consequently, we propose the multiple-stream predictor, a novel mechanism that deals with all branch types by combining single streams into long virtual streams. This proposal tolerates the prediction table access latency without requiring the complexity caused by additional hardware mechanisms like prediction overriding. Moreover, it provides high-performance results which are comparable to state-of-the-art fetch architectures but with a simpler design that consumes less energy.

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Section: Introductionmentioning

confidence: 99%

“…Therefore, most conditional branches in optimized codes are not taken, enlarging instruction streams [1], [2]. However, code layout optimizations are not enough for the stream fetch engine to completely overcome the need for an overriding mechanism [6].…”

Section: Introductionmentioning

confidence: 99%

Enlarging Instruction Streams

Desmet

Verbaeten

Joosen

et al. 2007

IEEE Trans. Comput.

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show abstract

“…The trace cache architecture [13,16,5] provides high fetch performance by buffering and reusing dynamic instruction traces. These traces are long enough to partially hide the prediction table access latency [18]. The rePLay microarchitecture [12] uses a front-end derived from the trace cache to generate even longer traces.…”

Section: Related Workmentioning

confidence: 99%

“…Taking into account realistic table access latencies, the best performance is achieved using the larger three cycle latency tables [17]. Although bigger predictors are slightly more accurate, their increased access delay harms processor performance.…”

Section: Stream Predictor Setupmentioning

confidence: 99%

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Reducing fetch architecture complexity using procedure inlining

Santana

Ramírez

Valero

Eighth Workshop on Interaction Between Compilers and Computer Architectures, 2004. INTERACT-8 2004.

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A survey of techniques for dynamic branch prediction

Mittal

2018

Concurrency and Computation

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Branch predictor (BP) is an essential component in modern processors since high BP accuracy can improve performance and reduce energy by decreasing the number of instructions executed on wrong-path. However, reducing the latency and storage overhead of BP while maintaining high accuracy presents significant challenges. In this paper, we present a survey of dynamic branch prediction techniques. We classify the works based on key features to underscore their differences and similarities. We believe this paper will spark further research in this area and will be useful for computer architects, processor designers, and researchers. KEYWORDSdynamic branch predictor, hybrid BP, neural BP, perceptron predictorside BP, pipelining, predictor accuracy, review, side BP, speculative execution, two-level BP INTRODUCTIONControl-changing instructions such as branches add uncertainty in the execution of dependent instructions and thus lead to large performance loss in pipelined processors. To offset their overhead, accurate prediction of branch outcomes is vital. Since branch misprediction incurs high latency (eg, 14 to 25 cycles 1 ) and wastes energy due to execution of instructions on wrong-path, an improvement in BP* accuracy can boost performance and energy efficiency significantly. For example, experiments on real processors showed that reducing the branch mispredictions by half improved the processor performance by 13%. 2Effective design and management of BPs, however, presents several challenges. Design of BP involves a strict tradeoff between area, energy, accuracy, and latency. An increase in BP complexity for improving accuracy may make it infeasible for implementation or offset its performance benefit. For example, a 512 KB perceptron predictor may provide lower instruction-per-cycle than its 32 KB version, 3 and a 2-cycle fully accurate BP may provide lower instruction-per-cycle than a 1-cycle partially inaccurate BP. 4 Further, due to its high access frequency, BP becomes a thermal hot-spot, 5 and hence, reducing its dynamic and leakage energy is important. Clearly, intelligent techniques are required for resolving these issues.Further, recently, researchers have demonstrated two security vulnerabilities viz., "Meltdown" and "Spectre," which exploit speculative execution feature of modern CPUs. 6-8 For example, Spectre vulnerability works on the observation that the speculative execution due to a branch misprediction may leave side effects, which can reveal sensitive data to attackers, eg, if the memory accesses performed during speculative execution depends on sensitive data, the resulting state of the cache forms a side-channel through which the sensitive data can be leaked. These vulnerabilities affect nearly every modern CPU. While avoiding speculative execution (eg, disabling branch prediction) can mitigate these vulnerabilities, it leads to significant performance loss. In light of these vulnerabilities and associated tradeoffs, a deeper study of branch predictors is definitely required. Contributions:In this ...

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Latency tolerant branch predictors

Abstract: The

Cited by 8 publications

References 25 publications

Enlarging Instruction Streams

Enlarging Instruction Streams

Reducing fetch architecture complexity using procedure inlining

A survey of techniques for dynamic branch prediction

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