The impact of atomic layer deposited SiO2passivation for high-k Ta1−xZrxO on the InP substrate

Mahata, Chandreswar; Oh, Il‐Kwon; Yoon, Chang Mo; Lee, Chang Wan; Seo, Jungmok; Algadi, Hassan; Sheen, Mi Hyang; Kim, Young Woon; Lee, Taeyoon

doi:10.1039/c5tc01890k

Cited by 16 publications

(13 citation statements)

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“…σv th D dos (7) where there is an energy difference ∆E between the trap level E T and the edge of the majority carrier band, v th is the majority carrier being thermally activated to obtain the average velocity, D dos is the effective density of states of the majority carrier band, k B is the Boltzmann constant, and T is the temperature [37]. The curves between conductivity (G/ω) and gate voltage for all samples are shown in Figure 7a-c.…”

Section: Conductivity-voltage Measurementsmentioning

confidence: 99%

“…Coulomb scattering and phonon scattering at the interface between the high-k gate dielectric and the channel material lead to a significant reduction in channel mobility, which severely affects the further increase in the speed of CMOS logic devices. Selecting channel materials with high mobility is an effective way to solve this problem [7]. Compared with conventional Si-based material CMOS devices, III-V group semiconductors have advantages due to their large switching speed and small dynamic power consumption [8].…”

Section: Introductionmentioning

confidence: 99%

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Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Lü

Yan

et al. 2021

Nanomaterials

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In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectron spectroscopy (XPS) measurements, it can be noted that ALD-derived Al2O3 interface passivation layer significantly prevents the appearance of substrate diffusion oxides and substantially optimizes gate dielectric performance. The leakage current experimental results confirm that the Sm2O3/Al2O3/InP stacked gate dielectric structure exhibits a lower leakage current density than the other samples, reaching a value of 2.87 × 10−6 A/cm2. In addition, conductivity analysis shows that high-quality metal oxide semiconductor capacitors based on Sm2O3/Al2O3/InP gate stacks have the lowest interfacial density of states (Dit) value of 1.05 × 1013 cm−2 eV−1. The conduction mechanisms of the InP-based MOS capacitors at low temperatures are not yet known, and to further explore the electron transport in InP-based MOS capacitors with different stacked gate dielectric structures, we placed samples for leakage current measurements at low varying temperatures (77–227 K). Based on the measurement results, Sm2O3/Al2O3/InP stacked gate dielectric is a promising candidate for InP-based metal oxide semiconductor field-effect-transistor devices (MOSFET) in the future.

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Section: Conductivity-voltage Measurementsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Lü

Yan

et al. 2021

Nanomaterials

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“…9 However, due to the introduction of high- k gate dielectrics, the electron mobility of MOSFET devices degrades inevitably, resulting from the influence of the Coulomb and phonon scatterings at the interface, which would definitively decrease the speed of the CMOS devices. 10 As a result, III–V compound semiconductors with high mobility are being investigated as one of the promising technology boosters to enhance MOSFET performance. Among III–V semiconductors, more attention has been paid to the investigation of GaAs-based channel materials for continuing the scaling of MOSFETs devices due to its larger band gap, higher breakdown field, and higher carrier mobility than other candidates.…”

Section: Introductionmentioning

confidence: 99%

Modulating the Interface Chemistry and Electrical Properties of Sputtering-Driven HfYO/GaAs Gate Stacks by ALD Pulse Cycles and Thermal Treatment

Liang

Wang

et al. 2019

ACS Omega

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In the current work, a detailed exploration on the cleaning effect of intrinsic oxide existing at the GaAs/HfYO interface by using an atomic-layer-deposition-derived trimethylaluminum (ALD TMA) precursor as functions of TMA pulse cycles and postannealing temperature has been evaluated via X-ray photoemission spectroscopy (XPS) measurements and electrical characterization. According to XPS analyses, it can be noted that the intrinsic As oxides, Ga oxides, and As 0 are effectively reduced from the HYO/GaAs gate stack after ALD TMA treatment with 20 pulse cycles. Meanwhile, optimized electrical parameters, such as the largest permittivity ( k ), the lowest hysteresis, and the minimum leakage density ( J g ), have also been obtained for the HfYO/GaAs gate stack with 20 pulse cycles of ALD TMA. Based on the optimized pulse cycles of 20 ALD TMA, postannealing temperature-dependent interface quality and electrical performance of GaAs-based devices based on the HfYO/GaAs gate stack have also been investigated. The HfYO/GaAs/Al metal-oxide semiconductor capacitor annealed at 300 °C with optimized pulse cycles of 20 displays the greatest dielectric constant of 38, the minimum J g of 3.28 × 10 –6 A cm –2 , and a small hysteresis of 0.01 V. Meanwhile, the leakage current transport mechanism at low temperature (77–327 K) has been discussed systematically.

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“…These constitute the active areas of the devices. A 3.1 nm-thick tunneling oxide is grown on top via dry oxidation, in order to minimize the trap density at the Si/oxide interface [307,308]. For the assembly of the molecular traps the underlying oxide is chemically modified with APTES, a type of aminosilane molecule used for the electrostatic self-organization of POM anions via the Layer-bylayer (LBL) process [309,29,304].…”

Section: Fabrication Of Capacitive Memory Cellsmentioning

confidence: 99%

“…These constitute the active areas of the devices. A 5 nm-thick tunneling oxide is grown on top via dry oxidation, in order to minimize the trap density at the Si/oxide interface [345,346] and be able to test topologies that require utilization of a tunneling oxide. For the Si wafers used as substrates, there is a strong absorption centered at 1105 cm −1 , typically attributed to the bulk Si-O-Si asymmetric stretching mode [347] and associated with interstitial oxygen in the Si bulk [286].…”

Section: Addressing the Materials Growth Challengesmentioning

confidence: 99%

Hybrid molecular solid state memories and electronic nanodevices based on polyoxometalates and other molecules of reversible redox activity

Μπάλλιου¹

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According to ITRS 2.0 2015, memory technologies will continue todrive pitch scaling and highest transistor count. As DRAM products areexpected to reach their scaling limits by 2024, and unless some majorbreakthrough occurs, flash memory is expected to lead the semiconduc-tor industry towards the next revolution in transistor density.Inspired from this fact, this work focuses on molecular flash mem-ories and logic switching molecular networks which, among all emerg-ing technology candidates, are considered particularly promising due totheir ability for reduction of size per cell and solution processing (lowcost, injection-printing friendly), conceptual compatibility with photonicaddressing due to molecular photosensitivity, multilevel storage, high in-formation density, quick write-read operations, low power consumption,mechanical flexibility, bottom-up fabrication logic (overcoming the litho-graphic patterning constrains), conceptual non-binary data representationand properties’ tunability through chemical tailoring.Molecular electronic devices are fabricated via a combination of bottom-up layer-by-layer nanofabrication and self-assembly with CMOS platformlithography in order to provide a low cost large-scale route towards ex-tension of the functional value of Si-based platforms.Tungsten Polyoxometalates (POM, [PW 12 O 40 ] 3− ) of the Keggin classare being self-arranged both on nanocrystal and hyperstructure level ina rational way resulting in layers of tunable spatial correlation length.The hyperstructures exhibit tunable valence and conduction bands and,hence, adjustable electronic properties directly related to the extent ofcrystallization of their building blocks.Dimensional crossover-driven insulator-to-semimetal transitions canbe enforced in these hyperstructures via tuning the extent of crystalliza-tion in solution. Being able to transport or confine charge at will, thesehyperstructures constitute ideal candidates for alternative molecule-basedsolution-printed circuitry components and transistor channels.Hybrid CMOS/molecular memory devices based on the parallel platearchitecture are fabricated, characterized and tested. Each memory el-ement contains a planar hyperstructure of molecules (typically several millions) that can store charge having multiple times the charge densityof a typical DRAM capacitor.Transition-metal-oxide hybrids composed of high surface-to-volumeratio Ta 2 O 5 matrices and tungsten POMs are investigated as a chargestorage composite in molecular nonvolatile capacitive memory cells. En-hanced internal scattering of carriers results in a memory window of 4.0V for the write state and a retention time around 10 4 s without blockingmedium.Differential distance of molecular trapping centers from the cells gateand electronic coupling to the space charge region of the underlying Sisubstrate are being identified as critical parameters for enhanced electrontrapping for the first time in such devices.The incorporation of a molecular-friendly blocking oxide that facili-tates long term retention while suppressing cross-talking, is performedthrough realization of a multi-functional oxide stack (SiO 2 /hybrid Ta 2 O 5 -POM transition metal oxide/Al 2 O 3 ) that takes parallel advantage of photo-nically-addressed phononic modes to boost information storage and reachmolecular states that were previously non-available. A 37 % informationdensity increase is attained via phononic pumping, while the memorywindow reaches 7.0 V, corresponding to ∼ 4 × 10 14 cm 2 charging nodesable to carry 65-195 μCb/cm 2 . Ability of multi-state addressing and writespeed of 10 ns are being documented for the packed cell.The fabricated high performance non-volatile memories are the firstdocumented CMOS-compatible long term (10 years criterion satisfaction)retention molecular capacitive cell of its kind.Following a different approach, brain-inspired, neural systems per-forming in networks and data-centric non-Von Neumann processing areamong the latest trends for non-conventional approaches in the semicon-ductor industry. We focus on hybrid molecular-nanoparticle networksthat exploit the massive parallelism of designless interconnected net-works of locally active components, obviating the need for expensivelithographic steps.Molecular multi-junction networks comprising of gold nanoparticles(AuNPs) of diam.∼1.4 nm, electronically linked by means of copper 3-diethylamino-1-propylsulphonamide sulfonic acid substituted phthalocya-nine (CuPcSu) molecules are fabricated and studied.When electrons flow through the non-linked nanoparticle arrays, theyexperience on-site Coulomb repulsion and are strongly localized, with lo-calization length (ξ=0.7 nm). Under dynamic excitation the system under-goes Coulomb oscillations, while the introduction of CuPcSu moleculesresults in the formation of a network of multiple molecular/Au nanojunc-tions and conductance increases by 5 orders of magnitude. This switching behavior functions on reversible red-ox reactions andpushes carriers in a weak localization state. In this state electrons spreadover several junctions and all temperature scaled current vs voltage curves,J/T^(1+α) vs eV/kT, collapse in one universal curve, characterizing the net-work and the extent of its disorder.On the other hand, the strongly non-linear I-V response and negativedifferential resistance of drop-cast nanojunction 3-d arrays makes themsuitable platforms for logic function exhibition. Common miniaturiza-tion bottlenecks such as capacitive crosstalk, are embraced as exploitablephysical processes, that can lead to robust computational functionality.The networks can be configured on-flight with pulses as quick as 10 nsto modify their resistance between two discrete levels. Both levels can beaddressed real time utilizing patterned nano-electrode pairs and readingvoltage of the order of 500 mV. The networks are able to perform as atwo-input “then-if” logic gates.

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The impact of atomic layer deposited SiO₂passivation for high-k Ta_1−xZr_xO on the InP substrate

Cited by 16 publications

References 53 publications

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Interface Optimization and Transport Modulation of Sm2O3/InP Metal Oxide Semiconductor Capacitors with Atomic Layer Deposition-Derived Laminated Interlayer

Modulating the Interface Chemistry and Electrical Properties of Sputtering-Driven HfYO/GaAs Gate Stacks by ALD Pulse Cycles and Thermal Treatment

Hybrid molecular solid state memories and electronic nanodevices based on polyoxometalates and other molecules of reversible redox activity

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