The ICAP parallel processor communications switch

Rana, Deepak Singh; Weems, Charles C.

doi:10.1109/iscas.1989.100307

Cited by 6 publications

(1 citation statement)

References 7 publications

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“…One of the challenges of building an analog-iterative decoder involves the design of these analog interleavers capable of performing any desired permutation of its symbols. The concepts involved in the design of analog interleavers are similar in many ways to those encountered in switching, for example in broadband photonic switching [9] and in multiprocessor memory architectures [10].…”

Section: Introductionmentioning

confidence: 99%

Programmable interleaver design for analog iterative decoders

Gaudet

Gaudet²,

Gulak³

2002

IEEE Trans. Circuits Syst. II

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Several programmable analog interleaver architectures for iterative decoders are proposed. The architectures are evaluated in terms of transistor count, path resistance, path capacitance, and programming logic. Interleavers built out of networks consisting of three layers of small crossbars are often deemed the best, reducing both switch count and capacitance by over 70% for an interleaver size of 100, as opposed to full crossbars, while maintaining full programmability.

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Section: Introductionmentioning

confidence: 99%

Programmable interleaver design for analog iterative decoders

Gaudet

Gaudet²,

Gulak³

2002

IEEE Trans. Circuits Syst. II

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NETRA: a hierarchical and partitionable architecture for computer vision systems

Choudhary

Patel

Ahuja

1993

IEEE Trans. Parallel Distrib. Syst.

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Abstract-Computer vision is regarded as one of the most complex and computationally intensive problems. In general, a Computer Vision System (CVS) attempts to relate scene(s) in terms of model(s). A typical CVS employs algorithms from a very broad spectrum such as such as numerical, image processing, graph algorithms, symbolic processing, and artificial intelligence. This paper presents a multiprocessor architecture+ called "NE-TRA," for computer vision systems. NETFLA is a highly flexible architecture. The topology of NETRA is recursively defined, and hence, is easily scalable from small to large systems. It is a hierarchical architecture with a tree-type control hierarchy. Its leaf nodes consists of a cluster of processors connected with a programmable crossbar with selective broadcast capability to provide the desired flexibility. The processors in clusters can operate in SIMD-, MIMD-or Systolic-like modes. Other features of the architecture include integration of limited data-driven computation within a primarily control flow mechanism, blocklevel control and data flow, decentralization of memory management functions, and hierarchical load balancing and scheduling capabilities. This paper also presents a qualitative evaluation and preliminary performance results of a cluster of NETRA.

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A feedback concentrator for the Image Understanding Architecture

Rana

Weems

[1990] Proceedings of the International Conference on Application Specific Array Processors

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The ICAP parallel processor communications switch

Cited by 6 publications

References 7 publications

Programmable interleaver design for analog iterative decoders

Programmable interleaver design for analog iterative decoders

NETRA: a hierarchical and partitionable architecture for computer vision systems

A feedback concentrator for the Image Understanding Architecture

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