2011 IEEE 20th Symposium on Computer Arithmetic 2011
DOI: 10.1109/arith.2011.27
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The IBM zEnterprise-196 Decimal Floating-Point Accelerator

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Cited by 27 publications
(13 citation statements)
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“…However, software operations run 100-1000 times slower than the corresponding binary operations implemented in hardware. For these reasons, in the revised IEEE standard 754 [5] support for decimal representation was added, and some companies are already commercializing processors which include decimal units [6], [7]. In this work, we show that we can accelerate with a decimal processor implemented on FPGA the accounting typically done by telephone companies.…”
Section: Introductionmentioning
confidence: 85%
“…However, software operations run 100-1000 times slower than the corresponding binary operations implemented in hardware. For these reasons, in the revised IEEE standard 754 [5] support for decimal representation was added, and some companies are already commercializing processors which include decimal units [6], [7]. In this work, we show that we can accelerate with a decimal processor implemented on FPGA the accounting typically done by telephone companies.…”
Section: Introductionmentioning
confidence: 85%
“…We will focus our attention here on designs using the conventional paradigm of CMOS digital gates although some alternative technologies [8,9] were also considered for decimal circuits at different points in time. Commercial hardware designs for decimal floating point additions were pioneered by IBM [10][11][12], followed by SilMinds [6,[13][14][15], then Fujitsu [16]. All of these commercial implementations use DPD.…”
Section: Specific Designsmentioning
confidence: 99%
“…Current commercial implementations of decimal floating point arithmetic are in servers [10][11][12]16] mainly targeting the financial sector. In the future, with the wider adoption of the ideas inherent in smart grids and the Internet-of-Things where many devices may communicate and conduct some financial transactions on behalf of their owners we might see more dedicated hardware for decimal in such embedded systems.…”
Section: Potential Embedded Systems Applicationsmentioning
confidence: 99%
“…The proposed design is synthesized and compared with the previous fastest work [8] in terms of the latency and area. It should be mentioned that although there are miscellaneous designs and architectures proposed for the sequential decimal multipliers (e.g., [3], [4] and [9]), we decided to pick up [8] as the reference for comparison since this is the fastest available in the literature.…”
Section: Introductionmentioning
confidence: 99%
“…The continuous growth of decimal FP arithmetic is gathering pace such that processors, nowadays, include special hardware accelerators for decimal FP arithmetic [3]. These units usually perform decimal addition, subtraction, multiplication and division in hardware, among which the latter two operations are the most complicated.…”
Section: Introductionmentioning
confidence: 99%