The IBM RISC System/6000 processor: Hardware overview

Bakoglu, H. B.; Grohoski, Greg; Montoye, Robert K.

doi:10.1147/rd.341.0012

Cited by 73 publications

(6 citation statements)

References 6 publications

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“…The initial models ranged in frequency from 20 MHz to 30 MHz [1] and achieved performance levels exceeding those of many of their contemporaries [2]. In 1993, the POWER2 microprocessor was introduced, operating initially at frequencies ranging from 55 MHz to 71.5 MHz [3].…”

Section: Introductionmentioning

confidence: 99%

POWER4 system microarchitecture

et al. 2002

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The IBM POWER4 is a new microprocessor organized in a system structure that includes new technology to form systems. The name POWER4 as used in this context refers not only to a chip, but also to the structure used to interconnect chips to form systems. In this paper we describe the processor microarchitecture as well as the interconnection architecture employed to form systems up to a 32-way symmetric multiprocessor.

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Section: Introductionmentioning

confidence: 99%

POWER4 system microarchitecture

et al. 2002

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“…Although these instructions are generated for the host’s architecture, which may not correspond to the ISA (i.e. RISC (Bakoglu et al, 1990)) of the Microgrid, it gives us a rough estimate of the amount of workload for the basic block. The technique of estimating the number of instructions in the basic block is shown in Figure 4.…”

Section: High-level Simulationmentioning

confidence: 99%

One-IPC high-level simulation of microthreaded many-core architectures

Uddin

2016

The International Journal of High Performance Computing Applica

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The microthreaded many-core architecture is comprised of multiple clusters of fine-grained multi-threaded cores. The management of concurrency is supported in the instruction set architecture of the cores and the computational work in application is asynchronously delegated to different clusters of cores, where the cluster is allocated dynamically. Computer architects are always interested in analyzing the complex interaction amongst the dynamically allocated resources. Generally a detailed simulation with a cycle-accurate simulation of the execution time is used. However, the cycle-accurate simulator for the microthreaded architecture executes at the rate of 100,000 instructions per second, divided over the number of simulated cores. This means that the evaluation of a complex application executing on a contemporary multi-core machine can be very slow. To perform efficient design space exploration we present a cosimulation environment, where the detailed execution of instructions in the pipeline of microthreaded cores and the interactions amongst the hardware components are abstracted. We present the evaluation of the high-level simulation framework against the cycle-accurate simulation framework. The results show that the high-level simulator is faster and less complicated than the cycle-accurate simulator but with the cost of losing accuracy.

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“…Currently, the most \'sOO architecture paradigrn in the design of commercial processors is the superscalar paradigrn. Examples of modern superscalar machines include the mM RlSC-6000 architecture [BW90], the Motorola 88110 [DA92], the Intel Pentium [AA93], the Hewlett-Packard PA7100 [AAD+93], the TFP [Hsu94] and the PowerPC [00H94,SD94].…”

Section: Horacementioning

confidence: 99%