An investigation of the performance of various instruction-issue buffer topologies

Jourdan, Stéphan; Sainrat, Pascal; Litaize, Daniel

doi:10.1109/micro.1995.476837

Cited by 3 publications

(3 citation statements)

References 18 publications

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“…Each cycle, multiple out-oforder instruction retirements can be made, freeing the physical registers to be reused in the renaming process. A previous study [11] has shown that configurations reported in table 1 of such out-of-order architectures give almost no performance loss over perfect configurations only limited by the size of the lookahead window, assuming an ideal-fetch mechanism and no misprediction. The instruction latencies used in the simulations were those of the PowerPC 604 [9].…”

Section: Yeh Marr and Partmentioning

confidence: 95%

“…To solve the whole problem, multiple non-consecutive basic blocks must be fetched in a single cycle as most basic blocks are only five instructions long. Indeed, the potential parallelism has been shown to be higher than six instructions per cycle in generalpurpose integer applications while assuming a perfect instruction-fetch mechanism [11]. A processor featuring such a mechanism would have to predict multiple targets and branch outcomes in a single cycle.…”

Section: Introductionmentioning

confidence: 99%

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Multiple-block ahead branch predictors

Seznec

Jourdan

Sainrat

et al. 1996

SIGOPS Oper. Syst. Rev.

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A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. This paper presents a novel costeffective mechanism called the two-block ahead branch predictor. Information from the current instruction block is not used for predicting the address of the next instruction block, but rather for predicting the block following the next instruction block.This approach overcomes the instruction fetch bottleneck exhibited by wide-dispatch "brainiac" processors by enabling them to e]ficiently predict addresses of two instruction blocks in a single cycle. Furthermore, pipelining the branch prediction process can also be done by means of our predictor for "speed demon" processors to achieve higher clock rate or to improve the prediction accuracy by means of bigger prediction structures.Moreover, and unlike the previously-proposed multiple predictor schemes, multiple-block ahead branch predictors can use any of the branch prediction schemes to perform the very accurate predictions required to achieve high-performance on superscalar processors.

show abstract

Section: Yeh Marr and Partmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

Multiple-block ahead branch predictors

Seznec

Jourdan

Sainrat

et al. 1996

SIGOPS Oper. Syst. Rev.

View full text Add to dashboard Cite

show abstract

“…The decentralization problem has also been tackled in other paradigms of which a good overview is given in [5]. Notice that a second level of decentralization is provided in the instruction window topology: an instruction window consists of multiple selection windows, see Figure 2, in order to reduce the complexity of the selection logic [2,12].…”

Section: Advantagesmentioning

confidence: 99%

On the feasibility of fixed-length block structured architectures

Eeckhout

Bosschere²,

Neefs³

Proceedings 5th Australasian Computer Architecture Conference. ACAC 2000 (Cat. No.PR00512)

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Scaling contemporary superscalar microarchitectures to higher levels of parallelism in future technologies seems to be impractical due to the increasing complexity [1]. In this paper, we show that a fixed-length block structured instruction set architecture (BSA), is capable of reducing the hardware complexity and is therefore feasible as an alternative architectural paradigm for traditional architectures with large virtual window sizes for future technologies. This is reached through two major interventions. First, statically grouping instructions from various basic blocks into larger atomic units of work with a fixed length, called blocks, makes fetching easier. Second, a decentralized microarchitecture reduces the processor core logic significantly, resulting in higher clock frequencies. The performance evaluation methodology used in this paper both considers IPC (number of useful instructions retired per clock cycle) and clock cycle period. In addition, a broad design space is explored by quantifying the influence of various microarchitectural parameters on overall performance.

show abstract

Multiple-block ahead branch predictors

et al. 1996

View full text Add to dashboard Cite

A basic rule in computer architecture is that a processor cannot execute an application faster than it fetches its instructions. This paper presents a novel cost-effective mechanism called the two-block ahead branch predictor. Information from the current instruction block is not used for predicting the address of the next instruction block, but rather for predicting the block following the next instruction block.This approach overcomes the instruction fetch bottle-neck exhibited by wide-dispatch "brainiac" processors by enabling them to efficiently predict addresses of two instruction blocks in a single cycle. Furthermore, pipelining the branch prediction process can also be done by means of our predictor for "speed demon" processors to achieve higher clock rate or to improve the prediction accuracy by means of bigger prediction structures.Moreover, and unlike the previously-proposed multiple predictor schemes, multiple-block ahead branch predictors can use any of the branch prediction schemes to perform the very accurate predictions required to achieve high-performance on superscalar processors.

show abstract

An investigation of the performance of various instruction-issue buffer topologies

Cited by 3 publications

References 18 publications

Multiple-block ahead branch predictors

Multiple-block ahead branch predictors

On the feasibility of fixed-length block structured architectures

Multiple-block ahead branch predictors

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