The Georgia Tech digital signal multiprocessor

Barnwell, T.P.; Madisetti, Vijay K.; McGrath, Stephen J. A.

doi:10.1109/78.224255

Cited by 15 publications

(2 citation statements)

References 25 publications

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“…Also, in the field of digital signal processing, multiprocessor DSP architectures become compelling solutions for high-performance applications such as packet telephony, 3G wireless infrastructure, and WiMAX [1]. Therefore, the designers proposed many multiprocessor DSP systems [2]- [8].…”

Section: Introductionmentioning

confidence: 99%

MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications

Sedaghati-Mokhtari

Bojnordi

Fakhraie

2007

2007 15th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems

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In this paper, we propose a multiprocessor DSP simulation toolkit suitable for performance evaluation of dataparallel applications like voice processing. The proposed toolkit uses the benefits of multi-level parallelism and clustering. Different DSP clusters are considered for the multiprocessor DSP simulation engine in which the DSP processors are grouped to cooperate. Satisfying the communication requirements, two global and local communication engines (GCE and LCE) implement the real behavior of intra-and inter-cluster communications. Using efficient abstraction levels for interconnections reduces the simulation time significantly. Abstract communication modeling, cycle-accurate behavior, and multi-level controlling are the most important features of the proposed simulation platform. Performance of the simulator is verified by standard single-and multi-channel voice processing applications such as ITU-T G.729a speech codec.

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Section: Introductionmentioning

confidence: 99%

MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications

Sedaghati-Mokhtari

Bojnordi

Fakhraie

2007

2007 15th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems

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“…Many approaches in the first class exploit only spatial concurrency [1][2][3][4]. The second class concurrency [5,6], based on cyclostatic scheduling, takes advantage of the stream processing nature of DSP to exploit temporal concurrency between iterations. While these can yield optimum solutions, their exponential search strategies preclude a practical implementation of a wide range of DSP applications.…”

Section: Introductionmentioning

confidence: 99%

AdEPar Integrated Simulation and Implementation Environment for DSP

Gümüşkaya

Örencik

1997

SIMULATION

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The AdEPar (Advanced Educational Parallel) integrated simulation and implementation environment for Digital Signal Processing (DSP) has been designed and implemented to serve as a test-bed for various scheduling, simulation, and code generation problems as well as a real-time implementation tool for DSP algorithms that could be mapped onto the proposed parallel pipelined architecture. The integrated environment fully exploits all types of concurrency present in DSP algorithms and addresses practical issues such as processor and memory constraints, architectural features of DSP processors in the target architectures, debugging of parallel programs, and development of high-level programming environments. The AdEPar software DSP environment is based on object-oriented programming techniques. Because DSP computation objects and graphics objects of AdEPar are separated from each other carefully, the software system portability is guaranteed. This programming approach saves time and effort to develop an environment based on a graphical user interface.

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