The Fabrication of CMOS Structures with Increased Immunity to Latchup Using the Two‐Step Epitaxial Process

Jastrzȩbski, L.; Corboy, J. F.; Soydan, R.; Pagliaro, R.; Magee, C. W.

doi:10.1149/1.2113724

Cited by 7 publications

(3 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The potential of the substrate also has a great influence on the characteristics of the device, which means the MOSFET is an actual connection of a four-port device. As shown in Figure 1., it is always realized by a p + ohmic region [6].…”

Section: Introductionmentioning

confidence: 99%

Simulation and optimization of metal gate CMOS process and circuit by TCAD

Tong

2023

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

The feature size of CMOS transistors is shrinking as the semiconductor industry and technology advance. This phenomenon will have significant research implications for how to change device performance and maintain good performance. As a result, this paper completed a design and simulation of the CMOS process flow using TCAD. It was discovered through a qualitative analysis of the simulation results that the transfer and input characteristics of NMOS transistors decrease proportionally with the scale factor.

show abstract

Section: Introductionmentioning

confidence: 99%

Simulation and optimization of metal gate CMOS process and circuit by TCAD

Tong

2023

J. Phys.: Conf. Ser.

View full text Add to dashboard Cite

show abstract

“…,Moreover, the circuit topography becomes increasingly severe as interconnect layers are added, imposing a practical limit of three levels of interconnection.if acceptable yield and reliability are to be obtained. resulting in reduced oxide lateral encroachment (2, 3), use of isolation trenches (4), the formation of devices on epitaxial layers of silicon (5,6) or sapphire (5), and the separation of transistors by amorphous insulators (SOI) (5,7,8). Some developments recently applied to the interconnect system include the use of a refractory silicide as a local interconnect (9) to reduce the number of contacts to silicon and increase packing density, improved schemes to contact the diffusion area (10), and the use of CVD tungsten to improve metal step coverage (11) and to fill contacts and vias selectively (12).…”

mentioning

confidence: 99%

A Scalable Multilevel Metallization with Pillar Interconnections and Interlevel Dielectric Planarization

Castel

Kulkarni

Riley

1990

J. Electrochem. Soc.

View full text Add to dashboard Cite

A multilevel metallization system, which results in smooth topography and high packing density by overcoming many of the limitations of the conventional approach, has been developed. In this scheme metallic pillars are used for interlevel wiring, instead of traditional contacts and vias. Refractory metal layers are employed at all levels as an etch stop/ diffusion barrier with a self-aligned metal silicide used to insure low contact resistance between conductor (aluminum) and silicon substrate. Planarized SiO2 is used as the dielectric at each level in which planarization of the dielehtric and exposure of the underlying metallization are achieved by the etchback technique using sacrificial photoresist films. This interconnection scheme can be extended to any number of levels of interconnection and may be readily scaled for use in submicron ULSI technologies.

show abstract

“…The first phase of ELO is selective epitaxial growth (SEG). In SEG the epi growth is terminated when the surface of the silicon films reaches the oxide surface (17)(18)(19)(20)(21)(22)(23)(24)(25)(26)(27)(28)(29)(30)(31)(32)(33). Problems encountered with defect generation, dependence of growth rate on pattern geometry, and properties of silicon oxide interfaces formed by silicon growing over or along the oxide are similar in the case of SEG and ELO.…”

mentioning

confidence: 99%

Issues and Problems Involved in Selective Epitaxial Growth of Silicon for SOI Fabrication

Jastrzȩbski

Corboy

Soydan

1989

J. Electrochem. Soc.

View full text Add to dashboard Cite

In the epitaxial lateral overgrowth (ELO) technique an SOI layer is formed by overgrowing oxide with CVD silicon seeded at the edges of an oxide island on single‐crystal silicon. In the ELO technique conventional epitaxial reactors are used for the production of epitaxial silicon. SOI films have low defect density (compared to other SOI approaches) and wafers supporting the ELO silicon are not warped. Electrical characteristics, such as mobility and lifetime of SOI/ELO films, are similar to homoepitaxial layer grown in the same reactor. In this paper the problems related to ELO and selective epitaxial growth (SEG) are discussed. Our present knowledge will be reviewed on the topics of: defect structure, dependence of the growth rate on pattern geometry, and overgrowth ratio. We will also discuss the electrical characteristics of ELO/ SEG films, with a special emphasis on the SiO2/normalsilicon interfacial properties (formed by CVD overgrowth). The process used to obtain SOI wafers with a continuous oxide layer underneath a silicon film will be described. The potential and the problems faced in preparing these layers will be discussed.

show abstract

The Fabrication of CMOS Structures with Increased Immunity to Latchup Using the Two‐Step Epitaxial Process

Abstract: not Available.

Cited by 7 publications

References 0 publications

Simulation and optimization of metal gate CMOS process and circuit by TCAD

Simulation and optimization of metal gate CMOS process and circuit by TCAD

A Scalable Multilevel Metallization with Pillar Interconnections and Interlevel Dielectric Planarization

Issues and Problems Involved in Selective Epitaxial Growth of Silicon for SOI Fabrication

Contact Info

Product

Resources

About