The Epsilon-2 hybrid dataflow architecture

Grafe, V.G.; Hoch, James E.

doi:10.1109/cmpcon.1990.63658

“…Recent dataow machines [12,22,25] allow several instructions, i.e., a thread, to be enabled by a single dataow synchronization. Registers are used to hold values with a lifetime of a single such thread, as these values need never be placed in the frame.…”

Section: Comparison With Other Modelsmentioning

confidence: 99%

“…The net reduction of synchronization events can be seen in the row labeled aborts which shows the number of unsatised entry count decrements, for the TL0 case, and match failures, for the TTDA, as a percentage of the total number of TTDA operations. The recent generation dataow machines [12,22,25] all support some form of thread, and the graph partitioning and elimination of redundant arcs used in TL0 compilation could be employed with similar benets.…”

Section: Threads Versus Dataow Graphsmentioning

confidence: 99%

Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

Culler¹,

Sah²,

Schauser³

et al. 1991

SIGOPS Oper. Syst. Rev.

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In this paper, we present a relatively primitive execution model for ne-grain parallelism, in which all synchronization, scheduling, and storage management is explicit and under compiler control. This is dened by a threaded abstract machine (TAM) with a multilevel scheduling hierarchy. Considerable temporal locality of logically related threads is demonstrated, providing an avenue for eective register use under quasi-dynamic scheduling.A prototype TAM instruction set, TL0, has been developed, along with a translator to a variety of existing sequential and parallel machines. Compilation of Id, an extended functional language requiring ne-grain synchronization, under this model yields performance approaching that of conventional languages on current uniprocessors.Measurements suggest that the net cost of synchronization on conventional multiprocessors can be reduced to within a small factor of that on machines with elaborate hardware support, such as proposed dataow architectures. This brings into question whether tolerance to latency and inexpensive synchronization require specic hardware support or merely an appropriate compilation strategy and program representation.

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“…Recent dataow machines [12,22,25] allow several instructions, i.e., a thread, to be enabled by a single dataow synchronization. Registers are used to hold values with a lifetime of a single such thread, as these values need never be placed in the frame.…”

Section: Comparison With Other Modelsmentioning

confidence: 99%

“…The net reduction of synchronization events can be seen in the row labeled aborts which shows the number of unsatised entry count decrements, for the TL0 case, and match failures, for the TTDA, as a percentage of the total number of TTDA operations. The recent generation dataow machines [12,22,25] all support some form of thread, and the graph partitioning and elimination of redundant arcs used in TL0 compilation could be employed with similar benets.…”

Section: Threads Versus Dataow Graphsmentioning

confidence: 99%

Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

Culler¹,

Sah²,

Schauser³

et al. 1991

View full text Add to dashboard Cite

In this paper, we present a relatively primitive execution model for ne-grain parallelism, in which all synchronization, scheduling, and storage management is explicit and under compiler control. This is dened by a threaded abstract machine (TAM) with a multilevel scheduling hierarchy. Considerable temporal locality of logically related threads is demonstrated, providing an avenue for eective register use under quasi-dynamic scheduling.A prototype TAM instruction set, TL0, has been developed, along with a translator to a variety of existing sequential and parallel machines. Compilation of Id, an extended functional language requiring ne-grain synchronization, under this model yields performance approaching that of conventional languages on current uniprocessors.Measurements suggest that the net cost of synchronization on conventional multiprocessors can be reduced to within a small factor of that on machines with elaborate hardware support, such as proposed dataow architectures. This brings into question whether tolerance to latency and inexpensive synchronization require specic hardware support or merely an appropriate compilation strategy and program representation.

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“…The most recent generation of dataflow machines (e.g., MIT's Monsoon, ETL's EM-4 [2], and Sandia's Epsilon-2 [3]) have shown how operands match can be accomplished with a simple hardware structure in two machine cycles. In Monsoon, the explicit storage for operands match is decided by the complier.…”

Section: Introductionmentioning

confidence: 99%

A pipeline bubbles reduction technique for the Monsoon dataflow architecture

Lai

¹

,

Tsai

²

1994

Proceedings of the Twenty-Seventh Hawaii International Conference on System Sciences HICSS-94

0

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This paper proposes two typesof new auziliary ory. The first type of the auxiliary matching store achieves high matching rate b y combining the LRU replacement algorithm and a simple match structure together. The second one achieves high match rate b y controlling strictly the number of active processes with an explicit hardware. Owing to some special characteristics of dynamic dataflow computing, this temporary storage must be designed based on the following principles: (a The number of the active processes must be limited. A) The related instructions must be arranged nearby. (c) The replacement of the match slot must be deterministic. can be applied to dynama frame-stnrctured mem-

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The Epsilon-2 hybrid dataflow architecture

Cited by 15 publications

References 5 publications

Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

A pipeline bubbles reduction technique for the Monsoon dataflow architecture

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