Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine

Abstract

In this paper, we present a relatively primitive execution model for ne-grain parallelism, in which all synchronization, scheduling, and storage management is explicit and under compiler control. This is dened by a threaded abstract machine (TAM) with a multilevel scheduling hierarchy. Considerable temporal locality of logically related threads is demonstrated, providing an avenue for eective register use under quasi-dynamic scheduling.A prototype TAM instruction set, TL0, has been developed, along with a translator to a variety of existing sequential and parallel machines. Compilation of Id, an extended functional language requiring ne-grain synchronization, under this model yields performance approaching that of conventional languages on current uniprocessors.Measurements suggest that the net cost of synchronization on conventional multiprocessors can be reduced to within a small factor of that on machines with elaborate hardware support, such as proposed dataow architectures. This brings into question whether tolerance to latency and inexpensive synchronization require specic hardware support or merely an appropriate compilation strategy and program representation.

Instruction scheduling for a tiled dataflow architecture

“…As with all dataflow architectures (e.g. [9,8,17,33,15,28,31,14,27,7,3]), an application is represented as a dataflow graph (DFG), with control dependences converted into data dependences. Nodes in the graph are instructions, and directed edges between them represent operand dependences.…”

Ποιοτική και ποσοτική μελέτη απόδοσης της παράλληλης αρχιτεκτονικής κατανεμημένης μνήμης PiSMA

“…Στην κατηγορία M[l,m,p] ανήκουν οι παραδοσιακές πολυνηματικές αρχιτεκτονικές που επιτρέπουν μόνο ένα νήμα για εκτέλεση σε κάθε κύκλο. Οι αρχιτεκτονικές ΤΑΜ [41] και April [6] για παράδειγμα είναι Μ[1,1,1]• Οι αρχιτεκτονικές ΕΜ-4 [81] και *Τ [117] είναι M[l,m,l] αφού σύμφωνα με τις αναφορές παρέχουν superscalar δυνατότητες. Η αρχιτεκτονική Tera [8] είναι Μ[1,1>3] αφού κάθε νήμα στην αρχιτεκτονική αποτελείται από μια ακολουθία από εντολές 3-λειτουργιών (3-operation instruction stream).…”

Performance bounds for distributed memory multithreaded architectures

“…In a traditional architecture, when a processor accesses a location in memory, it waits for the result, possibly after executing a few instructions that are independent of the memory operation. In a large multiprocessor, this wait may involve more than one hundred processor cycles [6] since the memory request may need to be transmitted across the communication network to a remote memory module, serviced, and then the result returned. Not surprisingly, the utilization of processors in such systems tends to be low.…”

“…Traditional multithreaded architectures [1,4,6,16] issue instructions from only one thread each cycle. The available instruction-level parallelism exploited by a single thread in the multithreaded execution is limited.…”

“…Several multithreaded architectures have been proposed which differ in the implementation of multithreading [1,4,5,6,8,10,12]. They differ in two basic aspects, in the number of instructions executed before switching to another thread (one, several, as many as possible), and the cause of context switching (every load, remote load).…”