The emerging power crisis in embedded processors

Abstract

It is widely acknowledged that even as VLSI technology advances, there is a looming crisis that is an important obstacle to the widespread deployment of mobile embedded devices, namely that of power. This problem can be tackled at many levels like devices, logic, operating systems, micro-architecture and compiler. While there have been various proposals for specific compiler optimizations for power, there has not been any attempt to systematically map out the space for possible improvements. In this paper, we quantitatively characterize the limits of what a compiler can do in optimizing for power using precise modeling of a state-of-the-art embedded processor in conjunction with a robust compiler. We provide insights to how compiler optimizations interact with the internal workings of a processor from the perspective of power consumption. The goal is to point out the promising and not so promising directions of work in this area, to guide the future compiler designer.

The effect of compiler optimizations on Pentium 4 power consumption

“…Chakrapani et al [6] also present a study into the effect of compiler optimization on the energy usage of an embedded processor. Their work targets an ARM embedded core and they use an RTL level model along with Synopsys Power Compiler to estimate power.…”

Task Migration for Energy Conservation in Real-Time Multi-processor Embedded Systems

“…DVS (Dynamic Voltage Scaling) [4][5][6][7] and DFS (Dynamic Frequency Scaling) are two approaches used to reduce power consumption [8]. Research in recent years has also expanded to green energy including the conversion of solar, wind, and tide energies into electricity [10][11][12].…”

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

“…With new design ideas optimization part into compiler is being equally weighed as having power efficient hardware. Chakrapani et al [82] identify two classes A and B of the compiler optimizations for energy reduction. Class A [82] consists of energy saving due to performance improvement such as reductions in the number of loads and stores, procedure cloning, loop unrolling, procedure inlining, and loop transformations.…”

“…Class A [82] consists of energy saving due to performance improvement such as reductions in the number of loads and stores, procedure cloning, loop unrolling, procedure inlining, and loop transformations. Class B [82] uses techniques like instruction scheduling; register pipelining, innovations in code selection to replace high power dissipating instructions with other instructions.…”