The Electrical Properties of Asymmetric Schottky Contact Thin-Film Transistors with Amorphous-$\hbox{In}_{2}\hbox{Ga}_{2}\hbox{ZnO}_{7}$

Rha, Sang Ho; Kim, Un Ki; Jung, Jongwan; Kim, Hyo Kyeom; Jung, Yoon Soo; Hwang, Eun Suk; Chung, Yoon Jang; Lee, Mijung; Choi, Jung-Hae; Hwang, Cheol Seong

doi:10.1109/ted.2012.2236558

Cited by 20 publications

(13 citation statements)

References 20 publications

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“…Next, as shown in Figure b,c, I D increases very little, only 0.15×, when L is increased 25×. These are consistent with the properties of SGTs that the device is controlled by the source region ( S ) and is less sensitive to L . This is an advantage over conventional TFTs where the drain current is affected by the shorter channel and thus is susceptible to device‐to‐device fluctuations due to fabrication variability .…”

Section: Structural and Electrical Characteristics Of Source‐gated Trsupporting

confidence: 78%

“…This is attributed to the 2D potential distribution in the semiconductor owing to the staggered‐electrode structure. This unusual effect has also been observed in other material systems . The output characteristics in Figure a–c show low saturation voltage, V D _ SAT , around 3 ± 1 V. It is noted that the V D _ SAT is similar for all S and L .…”

Section: Structural and Electrical Characteristics Of Source‐gated Trsupporting

confidence: 77%

“…This can be improved by reducing both the gate insulator and semiconductor thicknesses, thereby increasing g m . g o is small but non‐negligible in the operating range of V G (Figure a–c), although at very high gate bias, these transistors show negative g o due to the 2D potential distribution in the semiconductor . It follows that, for a limited span of V G , a very low g o could be achieved.…”

Section: Structural and Electrical Characteristics Of Source‐gated Trmentioning

confidence: 85%

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Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

et al. 2019

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Thin insulating layers are used to modulate a depletion region at the source of a thin‐film transistor. Bottom contact, staggered‐electrode indium gallium zinc oxide transistors with a 3 nm Al2O3 layer between the semiconductor and Ni source/drain contacts, show behaviors typical of source‐gated transistors (SGTs): low saturation voltage (VD_SAT ≈ 3 V), change in VD_SAT with a gate voltage of only 0.12 V V−1, and flat saturated output characteristics (small dependence of drain current on drain voltage). The transistors show high tolerance to geometry: the saturated current changes only 0.15× for 2–50 µm channels and 2× for 9‐45 µm source‐gate overlaps. A higher than expected (5×) increase in drain current for a 30 K change in temperature, similar to Schottky‐contact SGTs, underlines a more complex device operation than previously theorized. Optimization for increasing intrinsic gain and reducing temperature effects is discussed. These devices complete the portfolio of contact‐controlled transistors, comprising devices with Schottky contacts, bulk barrier, or heterojunctions, and now, tunneling insulating layers. The findings should also apply to nanowire transistors, leading to new low‐power, robust design approaches as large‐scale fabrication techniques with sub‐nanometer control mature.

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Section: Structural and Electrical Characteristics Of Source‐gated Trsupporting

confidence: 78%

Section: Structural and Electrical Characteristics Of Source‐gated Trsupporting

confidence: 77%

Section: Structural and Electrical Characteristics Of Source‐gated Trmentioning

confidence: 85%

See 1 more Smart Citation

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

et al. 2019

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“…Through linear extrapolation, the V th of the Pt, Al, and Al/PEI devices were extracted as −4.27, −20.26, and −15.75 V, respectively. In n-type oxide semiconductor TFT, it has been reported that when high–work-function source/drain materials forming a Schottky contact with an oxide semiconductor were used, the V th shifted to the positive direction with the increased SBH . Since Al forms a Schottky contact with the Cu 2 O layer, it has a negative shifted V th compared to Pt contact.…”

Section: Resultsmentioning

confidence: 99%

Modulation of the Al/Cu₂O Schottky Barrier Height for p-Type Oxide TFTs Using a Polyethylenimine Interlayer

Kim

Park

Min

et al. 2021

ACS Appl. Mater. Interfaces

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We introduced an organic interlayer into the Schottky contact interface to control the contact property. After inserting an 11-nm-thick polyethylenimine (PEI) interlayer between the aluminum (Al) source/drain electrode and the cuprous oxide (Cu2O) channel layer, the Cu2O thin-film transistors (TFTs) exhibited improved electrical characteristics compared with Cu2O TFTs without a PEI interlayer; the field-effect mobility improved from 0.02 to 0.12 cm2/V s, the subthreshold swing decreased from 14.82 to 7.34 V/dec, and the on/off current ratio increased from 2.43 × 102 to 1.47 × 103, respectively. Careful investigation of the contact interface between the source/drain electrode and the channel layer established that the performance improvements were caused by the formation of electric dipoles in the PEI interlayer. These electric dipoles reduced the Schottky barrier height by neutralizing the charges at the metal/oxide semiconductor interface, and the holes passed the reduced Schottky barrier by means of tunneling or thermionic injection. In this way, p-type oxide TFTs, which generally need a noble metal having a high work function as an electrode, were demonstrated with a low-work-function metal. As a basic application for logic circuits, a complementary inverter based on n-type indium–gallium–zinc oxide and p-type Cu2O TFTs was fabricated using only Al source/drain electrodes. This research achieved advances in low-cost circuit design by broadening the electrode metals available for the manufacture of p-type oxide semiconductor-based electronics.

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“…The subgap density of states (DOS) of amorphous ZTO was modeled with acceptor‐ and donor‐like trap states expressed as exponential or Gaussian functions. [ 17,18 ] The parameters used in the modeling of ZTO were shown in Table S1, Supporting Information. The simulated device structure was constructed with the same dimensions as the structure of the fabricated ZTO CTF.…”

Section: Resultsmentioning

confidence: 99%

Investigating the Reasons for the Difficult Erase Operation of a Charge‐Trap Flash Memory Device with Amorphous Oxide Semiconductor Thin‐Film Channel Layers

Kim

Kang

Jang

et al. 2021

Physica Rapid Research Ltrs

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A charge‐trap flash (CTF) device is fabricated using atomic‐layer‐deposited zinc tin oxide (ZTO) as an n‐type amorphous oxide semiconductor (AOS) channel layer and its program/erase characteristics are examined. When a positive voltage of 20 V is applied to the gate electrode, electrons are fluently injected into the adopted SiNx charge trap layer, resulting in a program operation showing a threshold voltage (Vth) shift of 3.7 V. However, even when −20 V is applied for up to 10 s, the trapped electrons are not detrapped. Instead, it is possible to recover Vth to its initial value only by the irradiation of white light. To understand this phenomenon, a ZTO CTF device is modeled using the technology computer‐aided design (TCAD) simulation package. The high hole injection barrier between the source/drain and the ZTO channel prohibits hole injection, which is the cause of the inefficient erasing. It is also confirmed that an AOS CTF with sufficient program and erase speed would be limited by the inherent energy band structure of AOS with its wide bandgap of over 3 eV. An alternative method of using the fringing field effect according to channel length scaling is proposed.

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The Electrical Properties of Asymmetric Schottky Contact Thin-Film Transistors with Amorphous-$\hbox{In}_{2}\hbox{Ga}_{2}\hbox{ZnO}_{7}$

Cited by 20 publications

References 20 publications

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

Modulation of the Al/Cu₂O Schottky Barrier Height for p-Type Oxide TFTs Using a Polyethylenimine Interlayer

Investigating the Reasons for the Difficult Erase Operation of a Charge‐Trap Flash Memory Device with Amorphous Oxide Semiconductor Thin‐Film Channel Layers

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The Electrical Properties of Asymmetric Schottky Contact Thin-Film Transistors with Amorphous-$\hbox{In}_{2}\hbox{Ga}_{2}\hbox{ZnO}_{7}$

Cited by 20 publications

References 20 publications

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

Novel Tunnel‐Contact‐Controlled IGZO Thin‐Film Transistors with High Tolerance to Geometrical Variability

Modulation of the Al/Cu2O Schottky Barrier Height for p-Type Oxide TFTs Using a Polyethylenimine Interlayer

Investigating the Reasons for the Difficult Erase Operation of a Charge‐Trap Flash Memory Device with Amorphous Oxide Semiconductor Thin‐Film Channel Layers

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Product

Resources

About

Modulation of the Al/Cu₂O Schottky Barrier Height for p-Type Oxide TFTs Using a Polyethylenimine Interlayer