The effect of copper trace routing on the drop test reliability of BGA modules

Abstract

The JEDEC drop test has become a popular method for the assessment of the dynamic mechanical reliability of 2nd level assemblies. It delivers repeatable results and is thus well suited for the development of a virtual lifetime model based on FEM simulations. Detailed experimental studies showed PCB copper trace fractures as the dominating failure mode. The virtual risk assessment applied a two steps approach (sub-modeling technique). The overall PCB motion was computed by a global model of the entire JEDEC board. In the second step, the copper trace load was investigated with a single component. The resultant plastic strain showed a clear dependency on the relation between copper trace routing and dominating PCB deformation. A strain map was derived which indicates the strain level as a pre-factor to each trace routing condition. The validity of the strain map concept was proven by comparison with experimental results. The strain map was able to precisely identify the f ailing interconnections at each component position. The combination of interconnection strain energy from the global model and the strain map was able to match the experimental sequence of failures across the JEDEC board exactly. A lifetime model was derived which is able to predict the cycles-to-failure of three different package types with less than 25% deviation to the tests. Hence, this lifetime model sets the ground for virtual prototyping that also includes the BGA drop test endurance

The influence of strain-rate dependent solder material models on the interconnection stress of BGA components in Jedec drop test

“…The root cause for PCB copper trace cracks is a wrong routing [13,14], which is not directly linked to the solder characteristics. But the solder material can influence the mechanical load and thus change the expected lifetime of the copper trace.…”