The Design of a Multi-Mode/Multi-System Capable Software Radio Receiver

Hueber, Gernot; Maurer, Linus; Strasser, Georg; Stuhlberger, R.; Chabrak, K.; Hagelauer, R.

doi:10.1109/iscas.2006.1693495

Cited by 12 publications

(4 citation statements)

References 7 publications

(5 reference statements)

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“…Similar to the aforementioned example design options 1, 2, and 3, various candidates in the architecture design space were evaluated before the final DFE architecture was proposed. A multitude of literatures deal with the DFE, including [2][3][4][5][6][7][8][9][11][12][13]17,[27][28][29][30], and many of them are based on the CIC filter, Farrow interpolator, and the FIR filter. However, most of them address only the simulated results and few of them explain the ASIC or FPGA implementation in detail.…”

Section: Discussionmentioning

confidence: 99%

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

et al. 2021

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A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

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Section: Discussionmentioning

confidence: 99%

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

et al. 2021

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“…Adaptation of RF receivers in SDRs to support multiple operation modes is a tedious task as to reconfigure the analog components is practically complicated [7]. Therefore, the flexibility is accomplished by reconfiguring the DFE, which changes the programming parameters of various embedded platforms and digital mixers [8], [9]. Different signal processing blocks can be shared by using DFE, facilitating the RoD, channel instantaneous conditions, and wireless communication models [10].…”

Section: Related Workmentioning

confidence: 99%

Adaptive Multi-Input Medium Access Control (AMI-MAC) Design Using Physical Layer Cognition for Tactical SDR Networks

et al. 2021

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Tactical software defined radio (SDR) networks demand stringent requirements of latency, throughput, and reliability. In the past, significant efforts have been made to achieve maximal efficiency with modifications and improvements either in an individual layer or through the cross-layer design of its working protocol. In this paper, we propose a novel cross-layer design consisting of adaptive multi-input medium access control (AMI-MAC) layer along with an intelligent channel allocation scheme supported by a multiband multimode physical layer. A cognitive engine further empowers this cross-layer design approach to achieve high throughput, improved quality of service (QoS), and adaptive range capabilities. The proposed physical layer exhibits a mixed use of narrowband and wideband waveforms accommodating different range requirements as per demanded QoS. The uniqueness of the proposed physical layer enables SDR to operate in hybrid topology by receiving multiple narrowband signals of different bandwidths with the same configuration of wideband RF front end. The proposed AMI-MAC design ensures a reduction in both control and data phase latency. MAC layer ensures the maximal utilization of the time and frequency spectrum. Bandwidth and delay optimization is also managed by the proposed trio of the physical layer, MAC, and cognition to reduce latency and achieve desired QoS. Simulation results are presented to show the superiority of the proposed design over conventional tactical radio MAC.

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“…Receiver approaches to cope with multi-mode functionality have been presented in [1]- [4]. Furthermore, the benefit of a digital frontend (DFE) for supporting different communication standards over a single receiver lineup is outlined in [5]- [7] and a combined solution of an analog and digital front-end on a single die has been demonstrated for the CDMA2000 standard in [8]. Using this mixed-signal approach, the present design was optimized to additionally cover the W-CDMA bands I, II and V, and GSM/EDGE in the low-and high band.…”

Section: Introductionmentioning

confidence: 99%

An adaptive multi-mode RF front-end for cellular terminals

Hueber¹,

Zipper²,

Stuhlberger³

et al. 2008

2008 IEEE Radio Frequency Integrated Circuits Symposium

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This paper presents a fully-integrated performanceon-demand receiver front-end for GSM/EDGE/W-CDMA/ CDMA2000 multi-mode cellular applications. The design's noise figure, linearity and selectivity are adapted depending on current environmental conditions and the selected standard to guarantee lowest overall power consumption. The single-chip zero-IF receiver comprises two self-matched LNAs for high/low-band, the demodulator and a fully-integrated ΔΣ−fractional−N PLL. The integration of I/Q-ADCs and a digital front-end (DFE) enables an efficient 3rd-order analog baseband filter. Accurate channel and matched filtering, sample-rate conversion and dynamic-range control are achieved in the DFE allowing for greater flexibility. In the absence of any blocker the performance of demodulator, VCO, analog baseband filter and DFE are adapted to reduce the current consumption up to 42 % versus the full-featured mode. The receiver has been fabricated in a 0.13 μm CMOS process and occupies 8 mm 2 die area. The design is verified by error-vector-magnitude (EVM) measurements exhibiting 3.9 % for W-CDMA and 3.1 % for CDMA2000.

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The Design of a Multi-Mode/Multi-System Capable Software Radio Receiver

Cited by 12 publications

References 7 publications

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

Adaptive Multi-Input Medium Access Control (AMI-MAC) Design Using Physical Layer Cognition for Tactical SDR Networks

An adaptive multi-mode RF front-end for cellular terminals

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