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To effectively compute convolutional layers, a complex design space must exist (e.g., the dataflow techniques associated with the layer parameters, loop transformation techniques, and hardware parameters). For efficient design space exploration (DSE) of various dataflow techniques, namely, the weight-stationary (WS), output-stationary (OS), row-stationary (RS), and no local reuse (NLR) techniques, the processing element (PE) structure and computational pattern of each dataflow technique are analyzed. Various performance metrics are calculated, namely, the throughput (in giga-operations per second, GOPS), computation-to-communication ratio (CCR), on-chip memory usage, and off-chip memory bandwidth, as closed-form expressions of the layer and hardware parameters. In addition, loop interchange and loop unrolling techniques with a double-buffer architecture are assumed. Many roofline model-based simulations are performed to explore relevant dataflow techniques for a wide variety of convolutional layers of typical neural networks. Through simulation, this paper provides insights into the trends in accelerator performance as the layer parameters change. For convolutional layers with large input and output feature map (ifmap and ofmap) widths and heights, the GOPS of the NLR dataflow technique tends to be higher than that of the techniques. For convolutional layers with low weight and ofmap widths and heights, the RS dataflow technique achieves optimal GOPS and on-chip memory usage. In the case of convolutional layers with small weight widths and heights, the GOPS of the WS dataflow technique tends to be high. In the case of convolutional layers with small ofmap widths and heights, the OS dataflow technique achieves optimal GOPS and on-chip memory usage. INDEX TERMS Accelerator, convolutional neural networks (CNNs), dataflow techniques, roofline, simulation, processing element (PE), design space exploration (DSE), field-programmable gate array (FPGA)

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

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With a target to maximize the throughput, a fast link rate adaptation algorithm for IEEE 802.11a/b/g/n/ac is proposed, which is basically preamble based and can adaptively compensate for the discrepancy between transmitter and receiver radio frequency performances by exploiting the acknowledgment signal. The target system is a 1 × 1 wireless local area network chip with no null data packet or sounding. The algorithm can be supplemented by automatic rate fallback at the initial phase to further expedite rate adaptation. The target system receives wireless channel coefficients and previous packet information, translates them to amended signal-to-noise ratios, and then, via the mean mutual information, selects the modulation and coding scheme with the maximum throughput. Extensive simulation and wireless tests are carried out to demonstrate the validity of the proposed adaptive preamble-based link adaptation in comparison with both the popular automatic rate fallback and ideal link adaptation. The throughput gain of the proposed link adaptation over automatic rate fallback is demonstrated over various packet transmission intervals and Doppler frequencies. The throughput gain of the proposed algorithm over ARF is 46% (15%) for a 1-tap (3-tap) channel over 10 m–250 m (16 m–160 m) normalized Doppler frequencies. Assuming a 3-tap channel and 30 m–50 m normalized Doppler frequencies, the throughput of the proposed algorithm is about 31 Mbps, nearly the same as that of ideal link adaptation, whereas the throughput of ARF is about 24 Mbps, leading to a 30% throughput gain of the proposed algorithm over ARF. The firmware is implemented in C and on Xilinx Zynq 7020 (Xilinx, San Jose, CA, USA) for wireless tests.

The performance of a hardware accelerator is often limited by the communication bandwidth between local on-chip memories and DRAM across on-chip bus. In this paper, a system-level performance estimation algorithm is newly proposed for evaluating the communication performance of direct memory access (DMA) controlled accelerators. The proposed algorithm can estimate the communication performance accurately for both DRAM-limited and bus-limited cases. In detail, the communication performance

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