The design of a low-power high-speed current comparator in 0.35-&amp;#x003BC;m CMOS technology

Ziabakhsh, Soheil; Alavi-Rad, Hosein; Alavi-Rad, Mohammad; Mortazavi, Mohammad

doi:10.1109/isqed.2009.4810278

Cited by 12 publications

(5 citation statements)

References 11 publications

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“…In the early of 1990's, it was reported researchers that water trees in XLPE cable insulation can produce harmonics in the loss current when AC high voltage is applied to the cable [1,2]. The basic configuration of the measuring system developed in this study is shown in Figure 2, This system consists of a current comparator based high voltage capacitance bridge and a computer measuring and analysis system.…”

Section: Measurement Of Harmonicsmentioning

confidence: 99%

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The Applications of Current Comparators in the Measurements on High Voltage Insulation

Fei

Dong

Chen

et al. 2016

MATEC Web of Conferences

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Abstract. This paper describes the basic structure of the current comparator used for high voltage insulation measurements. Further applications for the current comparator in high voltage insulation are investigated and developed. A measuring system for the measurement of harmonics in the loss current of water tree aged insulation is described, as well as the principles to measure partial discharges with the current comparator bridge. A new system for the measurement of the DC component in the leakage current of insulation is developed and presented. The results of experiments on XLPE cable insulation are also given.

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Section: Measurement Of Harmonicsmentioning

confidence: 99%

“…In the early 1990's, Japanese and Canadian researchers deve1oped the current comparator bridge further to apply it in laboratory tests for the measurement of harmonics in the1oss current of water tree aged XLPE cable insulation [1,2].…”

Section: Introductionmentioning

confidence: 99%

The Applications of Current Comparators in the Measurements on High Voltage Insulation

Fei

Dong

Chen

et al. 2016

MATEC Web of Conferences

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“…External biased signals VB, VB I AS, V 0 and VREF can be adjusted to mitigate mismatch and offset errors in the circuit and produces voltage evolution on the output node quadratic with time. Several other current comparators from present literature [7]- [9] are simulated and the Current Steering Comparator outperforms others for very low signal currents.…”

Section: Current Comparatormentioning

confidence: 99%

Low power fast cryogenic CMOS circuit for digital readout of single electron transistor

Das

Lehmann

2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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We present a cryogenic CMOS circuit with signif icant performance improvements compared to previously pro posed single-shot Single Electron Transistor readout circuit. The new readout architecture developed on commercial O.5J.tm SOl CMOS process is desinged to operate at 4.2K temperature and detect the SET signal current as low as 200pA. In addition to very low signal levels, the design process is complicated due to severe power consumption limitations at low temperature and J.tV level drain-source compliance requirement of the SET. The design addresses the low-temperature CMOS irregularities found in published literature and even under the design restrictions andSET specifications, our circuit shows successful digital detection of a SET event with only'" 520ns delay and consumes as low as 761' W power. In addition to speed improvement over previous design (detection time more than l0J.ts), this design is more robust and tolerant to biasing variations.

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“…Further, [31]- [34] employ various biasing techniques to reduce input impedance and hence achieve higher speeds of operation while maintaining lower power consumption. Specifically, simple biasing method is used in [31] and [33] whereas [32] uses negative feedback scheme at the transimpedance stage with an aim to achieve a very large loop-gain while maintaining the transformed voltage signal gain at the lowest swing in order to achieve speed…”

Section: Introductionmentioning

confidence: 99%

High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

Bhatia

Pandey

Bhattacharyya

2016

IJECE

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A novel power-speed efficient current comparator is proposed in this paper. It comprises of only CMOS inverters in its structure, employing a simple biasing method. The structure offers simplicity of design. It posesses the very desirable features of high speed and low power dissipation, making this structure a highly desirable one for various current mode applications. The simulations have been performed using UMC 90 nm CMOS technology and the results demonstrate the propagation delay of about 3.1 ns and the average power consumption of 24.3 µW for 300 nA input current at supply voltage of 1V.

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The design of a low-power high-speed current comparator in 0.35-μm CMOS technology

Cited by 12 publications

References 11 publications

The Applications of Current Comparators in the Measurements on High Voltage Insulation

The Applications of Current Comparators in the Measurements on High Voltage Insulation

Low power fast cryogenic CMOS circuit for digital readout of single electron transistor

High Speed Power Efficient CMOS Inverter Based Current Comparator in UMC 90 nm Technology

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