2020
DOI: 10.1007/s10825-020-01550-1
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The design and analysis of a CMOS-compatible silicon photonic ON–OFF switch based on a mode-coupling mechanism

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Cited by 4 publications
(2 citation statements)
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“…The dimensions of the silicon device layer is 500×220 nm with slab height of 90 nm. The upper and lower cladding of SiO 2 with a thickness of 2 µm is considered and the transverse-electric (TE) polarization is employed in the simulation [8]. In the proposed SoI platform, silicon device layer (n 1 =3.54 at 1550 nm) is covered by SiO 2 cladding layer (n 2 =1.54 at 1550 nm), this structure results in a 40% high index contrast ratio.…”
Section: Reconfigurable Quantum Photonic Gatementioning
confidence: 99%
See 1 more Smart Citation
“…The dimensions of the silicon device layer is 500×220 nm with slab height of 90 nm. The upper and lower cladding of SiO 2 with a thickness of 2 µm is considered and the transverse-electric (TE) polarization is employed in the simulation [8]. In the proposed SoI platform, silicon device layer (n 1 =3.54 at 1550 nm) is covered by SiO 2 cladding layer (n 2 =1.54 at 1550 nm), this structure results in a 40% high index contrast ratio.…”
Section: Reconfigurable Quantum Photonic Gatementioning
confidence: 99%
“…These inherent problems does not allow the directional coupler to completely transfer the power/intensity to adjacent waveguide and leads to ≈100% transfer. Due to the advanced fabrication technology, these inherent problems are in control, hence we focus on the reconfigurable photonic structures with directional couplers [8][9][10][11].…”
Section: Introductionmentioning
confidence: 99%