The D‐C MOSFET Dopant Profile Method

Buehler, M.

doi:10.1149/1.2129736

Cited by 19 publications

(4 citation statements)

References 8 publications

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“…For ion-implanted layers, test structures are used to determine the doping profile and information about residual substrate impurities [4]. The dopant density and depletion width can be determined using transistors, capacitors or diodes [9]. These structures also allow C-V…”

Section: Methodsmentioning

confidence: 99%

Review of semiconductor microelectronic test structures with applications to infrared detector materials and processes

Kopanski¹,

Schuster²

1993

Semicond. Sci. Technol.

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The impact of microelectronic test structures, as they have been apDlied to silicon integrated circuits (ICS) and gallium arsenide monolithic microwave integrated circuits (MMICS), is reviewed. General principles for the use of test structures with possible applications to infrared (IR) detector technology based on HgCdTe and other materials are emphasized. The uses of test structures for Si and GaAs, test chip design methodology and some examples of how test structures have been applied for process control and to increase yield are discussed. Specific test structures and techniques that have been applied to IR detectors are also reviewed. The basic design considerations and measurements possible with each class of test structure are discussed. The important experience of the Si and GaAs industries, applicable to IR detectors, is that significant yield improvement is possible with improved process control using test structures. Increased research efforts to expand the apolications of test structures to IR detector manufacture are indicated. ' *Contribution of the National Institute oi Standards and Technology: not subject to copyright.

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Section: Methodsmentioning

confidence: 99%

Review of semiconductor microelectronic test structures with applications to infrared detector materials and processes

Kopanski¹,

Schuster²

1993

Semicond. Sci. Technol.

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“…Analysis of dopant distribution.--To verify the existence of the buried n-region in the SPIRRIT films, we measured the channel dopant profiles for PMOS transistors from both lots using the dc MOSFET profiling method (12). Although this technique cannot be used to measure an n-type dopant region in an NMOS device directly, the presence of a spurious n-region in the PMOS devices may indicate that the entire film is contaminated by an unknown n-type dopant.…”

Section: Nmosmentioning

confidence: 99%

A Complementary Metal Oxide Semiconductor Process in Epitaxially Regrown Silicon over Oxide

Leung

Cole

Cobert

et al. 1991

J. Electrochem. Soc.

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A new solid-phase epitaxy technique, solid-phase isolated regrowth for radiation-immune technology (SPIRRIT), is described that has speed, density, and radiation-immunity advantages over bulk Si circuit technologies. Partial isolation between source and drain areas and substrate is achieved by incorporating a buried oxide layer into the metal oxide semiconductor (MOS) structures during complementary metal oxide semiconductor (CMOS) processing. Seeded epitaxial regrowth of an amorphized silicon film creates the active transistor channels. Rutherford backscattering and x-ray diffraction measurements indicate that the current amorphization and recrystallization process yields crystalline material to a depth of 0.2 vm, with some residual subsurface damage in the depth range from 0.2 to 0.5 ~m. PMOS SPIRRIT transistors have demonstrated near-bulk performance. NMOS SPIRRIT transistors displayed high transconductances, but also exhibited large leakage currents. The leakage is attributed to a spurious donor region in the recrystallized film.Silicon on insulator (SOD integrated circuit technologies have potential advantages in speed, packing density, and power dissipation compared to conventional bulk approaches, resulting from the reduced junction areas and the ideal isolation provided by the insulating substrate. In addition, SOI technologies are attractive for space applications, due primarily to their inherent radiation immunity. However, the complexities of material preparation for many SOI technologies can add considerably to chip costs and may introduce additional device failure modes, thereby reducing circuit reliability. The solid phase isolated regrowth for radiation immune technology (SPIR-RIT) technique, currently under study at The Aerospace Corporation, is an alternative to SOI technologies. It addresses these issues by incorporating a buried oxide into the MOS transistor structure during CMOS processing. The SPIRRIT fabrication sequence employs CMOS-c0m-patible process steps such as localized oxidation of silicon (LOCOS), polysilicon deposition, silicon ion implantation, and thermal annealing to form transistors with source and drain areas that are isolated from the bulk silicon substrate by a buried oxide. The SPIRRIT technique is compatible with standard production equipment and procedures. It requires a low-pressure chemical vapor deposition (LPCVD) reactor for film deposition, an ion implanter for amorphization, and a furnace for annealing the film. In other respects, it utilizes conventional CMOS processing procedures. In this way, the speed, density, and radiation immunity improvements over bulk CMOS technologies can be realized without substantial cost or complexity penalties. This method therefore appears to be a promising approach for production.Cross-sectional and plan views of the SPIRRIT structure are shown in Fig. 1. The channel of the MOS device is fabricated over the seed window and electrically connected to the buried shield through the seed. The source and drain regions are formed in the th...

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“…In general, profiles determined by this technique are limited to distances from the surface greater than three times the Debye length for the material [23]. Further description of the measurement technique and analysis is found elsewhere [23][24][25][26][27]. The design dimensions for the MOSFET gate are L = 10 pm and W = 440 pm.…”

Section: Dopant Profiling Measurementsmentioning

confidence: 99%

An NMOS test chip for a course in semiconductor parameter measurements

Roenker¹,

Linholm²

1984

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This report describes an NMOS test chip, NBS-40, which was developed to be used in graduate level electronics engineering courses involving semiconductor parameter measurements associated with the fabrication of integrated circuits. The 35 test structures included in the test chip and their use in materials, device, and process parameter measurements are described. Details of the silicon gate NMOS process used in the chip fabrication are also provided.

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The D‐C MOSFET Dopant Profile Method

Cited by 19 publications

References 8 publications

Review of semiconductor microelectronic test structures with applications to infrared detector materials and processes

Review of semiconductor microelectronic test structures with applications to infrared detector materials and processes

A Complementary Metal Oxide Semiconductor Process in Epitaxially Regrown Silicon over Oxide

An NMOS test chip for a course in semiconductor parameter measurements

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