The current-carrying corner inherent to trench isolation

Bryant, A.; Haensch, Wilfried; Geissler, S.; Mandelman, J.; Poindexter, D.; Steger, M.

doi:10.1109/55.225596

Cited by 35 publications

(11 citation statements)

References 5 publications

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“…This device has a negative effect on performance, causing a ''kink effect'' [28] in the MOSFET transfer characteristics (Fig. As in the case of LOCOS, topography complicates lithography.…”

Section: The Planarization Step In Detailmentioning

confidence: 99%

Shallow Trench Isolation Chemical Mechanical Planarization

Stefanov

Schwalke

2007

Microelectronic Applications of Chemical Mechanical Planarization

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“…This device has a negative effect on performance, causing a ''kink effect'' [28] in the MOSFET transfer characteristics (Fig. As in the case of LOCOS, topography complicates lithography.…”

Section: The Planarization Step In Detailmentioning

confidence: 99%

Shallow Trench Isolation Chemical Mechanical Planarization

Stefanov

Schwalke

2007

Microelectronic Applications of Chemical Mechanical Planarization

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“…It replaced local oxidation of silicon over which it has several advantages such as higher packing density, tighter design rules, and higher yields [1]. However, STI can cause a parasitic current from drain to source of the device due to the edge effects [2]. The amount of this parasitic current depends on the following technological parameters: exact shape of the STI edge, radius of the rounded edge (if rounded), amount of STI recess, etc.…”

Section: Introductionmentioning

confidence: 98%

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

Khandelwal

Agarwal

Duarte

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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We enhance the capability of industry standard compact model BSIM6 to model the parasitic current I edge at the shallow trench isolation edge. Accurate, efficient, and scalable model for I edge is developed by finding the key differences between I edge and main device drain current (I main ). It is found that I edge has a different sub-threshold slope, body-bias coefficient, and short-channel behavior as compared to I main . These important effects along with their dependencies on device geometry, bias conditions, and temperature are accounted for in the model. The model is in excellent agreement with experimental data verifying its scalability and readiness for production level usage.

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“…The fringing gate fields at the STI edge enhance carrier inversion, thus creating a parallel conduction corner channel with a lower threshold voltage than that of the center channel , resulting in the so-called subthreshold "hump" in the -characteristics [2]- [9]. Various corner rounding techniques have been used to minimize such a subthreshold hump which increases standby currents [3].…”

Section: Introductionmentioning

confidence: 99%

Enhanced low-temperature corner current-carrying inherent to shallow trench isolation (STI)

Niu

Cressler²,

Mathew³

et al. 1999

IEEE Electron Device Lett.

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The subthreshold hump in the current-voltage (I0V ) characteristics caused by the current-carrying corner in shallow-trench-isolated (STI) n-channel MOSFET's is significantly enhanced at reduced temperatures. Numerical simulations show that the sensitivity of the corner channel's threshold voltage to temperature is smaller than that of the center channel's threshold voltage. This, together with the reduced subthreshold swing at low temperatures, contribute to an enhanced subthreshold hump, and is potentially important for emerging cryogenic applications.

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The current-carrying corner inherent to trench isolation

Cited by 35 publications

References 5 publications

Shallow Trench Isolation Chemical Mechanical Planarization

Shallow Trench Isolation Chemical Mechanical Planarization

Modeling STI Edge Parasitic Current for Accurate Circuit Simulations

Enhanced low-temperature corner current-carrying inherent to shallow trench isolation (STI)

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